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Searched refs:mmUVD_RB_BASE_LO2 (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h39 #define mmUVD_RB_BASE_LO2 0x3c21 macro
H A Duvd_7_0_offset.h84 #define mmUVD_RB_BASE_LO2 … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h206 #define mmUVD_RB_BASE_LO2 … macro
H A Dvcn_2_5_offset.h561 #define mmUVD_RB_BASE_LO2 … macro
H A Dvcn_2_0_0_offset.h918 #define mmUVD_RB_BASE_LO2 … macro
H A Dvcn_3_0_0_offset.h891 #define mmUVD_RB_BASE_LO2 … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
1006 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1314 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
H A Dvcn_v2_0.c68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
1150 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1307 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
H A Dvcn_v3_0.c75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
1357 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_start()
1737 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
H A Dvcn_v2_5.c71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
1341 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1696 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
H A Duvd_v6_0.c876 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v6_0_start()
H A Duvd_v7_0.c1125 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); in uvd_v7_0_start()