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Searched refs:mmUVD_RB_BASE_LO (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h44 #define mmUVD_RB_BASE_LO 0x3c26 macro
H A Duvd_7_0_offset.h94 #define mmUVD_RB_BASE_LO … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h216 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_2_5_offset.h551 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_2_0_0_offset.h928 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_3_0_0_offset.h881 #define mmUVD_RB_BASE_LO … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1141 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1297 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
2013 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), in vcn_v2_0_start_sriov()
H A Dvcn_v3_0.c73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1348 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1480 mmUVD_RB_BASE_LO), in vcn_v3_0_start_sriov()
1727 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
H A Dvcn_v2_5.c69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1332 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1502 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1686 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v1_0.c57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
999 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1307 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
H A Duvd_v7_0.c923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
1118 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
H A Duvd_v6_0.c869 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v6_0_start()