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Searched refs:mmRLC_MEM_SLP_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1156 #define mmRLC_MEM_SLP_CNTL 0x30D8 macro
H A Dgfx_7_0_d.h1247 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
H A Dgfx_7_2_d.h1260 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
H A Dgfx_8_0_d.h1349 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
H A Dgfx_8_1_d.h1351 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c4962 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4965 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4991 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4994 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5300 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v8_0.c709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5452 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5669 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5672 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v7_0.c3584 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3587 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
H A Dgfx_v10_0.c7922 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7925 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7955 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7958 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
8487 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5969 #define mmRLC_MEM_SLP_CNTL … macro
H A Dgc_9_1_offset.h6191 #define mmRLC_MEM_SLP_CNTL … macro
H A Dgc_9_2_1_offset.h6155 #define mmRLC_MEM_SLP_CNTL … macro
H A Dgc_10_1_0_offset.h9301 #define mmRLC_MEM_SLP_CNTL … macro
H A Dgc_10_3_0_offset.h9101 #define mmRLC_MEM_SLP_CNTL … macro