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Searched refs:mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h3650 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h10319 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h5677 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_1_0_offset.h5436 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h12653 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6615 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h13964 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro