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Searched refs:mmMPCC0_MPCC_CONTROL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h3578 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_3_offset.h6145 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h10251 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h5605 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_1_0_offset.h5368 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h12585 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h6543 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h13896 #define mmMPCC0_MPCC_CONTROL_BASE_IDX … macro