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Searched refs:mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h2593 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_1_offset.h4803 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h4573 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_1_0_offset.h4524 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h5347 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h5511 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h5398 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … macro