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Searched refs:mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h9039 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
H A Ddcn_2_1_0_offset.h10942 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
H A Ddcn_1_0_offset.h9378 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
H A Ddcn_3_0_2_offset.h10681 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
H A Ddcn_2_0_0_offset.h12029 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
H A Ddcn_3_0_0_offset.h11825 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h11151 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … macro