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Searched refs:mmCP_VMID_RESET (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h308 #define mmCP_VMID_RESET 0x30b3 macro
H A Dgfx_7_2_d.h310 #define mmCP_VMID_RESET 0x30b3 macro
H A Dgfx_8_0_d.h341 #define mmCP_VMID_RESET 0x30b3 macro
H A Dgfx_8_1_d.h341 #define mmCP_VMID_RESET 0x30b3 macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c4980 gfx_v7_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp); in gfx_v7_0_reset_kgq()
4993 gfx_v7_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff); in gfx_v7_0_reset_kgq()
4994 gfx_v7_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0); in gfx_v7_0_reset_kgq()
H A Dgfx_v8_0.c6895 gfx_v8_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp); in gfx_v8_0_reset_kgq()
6908 gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff); in gfx_v8_0_reset_kgq()
6909 gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0); in gfx_v8_0_reset_kgq()
H A Dgfx_v9_0.c7219 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); in gfx_v9_0_reset_kgq()
7233 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffff); in gfx_v9_0_reset_kgq()
7235 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0); in gfx_v9_0_reset_kgq()
H A Dgfx_v10_0.c3824 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp); in gfx_v10_0_kiq_reset_hw_queue()
9523 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); in gfx_v10_0_reset_kgq()
9528 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); in gfx_v10_0_reset_kgq()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2591 #define mmCP_VMID_RESET … macro
H A Dgc_9_1_offset.h2861 #define mmCP_VMID_RESET … macro
H A Dgc_9_2_1_offset.h2795 #define mmCP_VMID_RESET … macro
H A Dgc_10_1_0_offset.h4933 #define mmCP_VMID_RESET … macro
H A Dgc_10_3_0_offset.h4592 #define mmCP_VMID_RESET … macro