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Searched refs:mmCP_MEC_CNTL (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h52 { 0x50000000, mmCP_MEC_CNTL },
1502 { 0x00000000, mmCP_MEC_CNTL },
1503 { 0x00000000, mmCP_MEC_CNTL },
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c192 mmCP_MEC_CNTL); in smu8_load_mec_firmware()
195 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp); in smu8_load_mec_firmware()
H A Dfiji_smumgr.c213 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in fiji_start_avfs_btc()
H A Dpolaris10_smumgr.c111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c1211 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data); in kgd_gfx_v9_hqd_reset()
1212 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0); in kgd_gfx_v9_hqd_reset()
H A Dgfx_v7_0.c2638 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
2640 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | in gfx_v7_0_cp_compute_enable()
4589 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
H A Dgfx_v9_0.c211 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
3436 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable()
3438 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, in gfx_v9_0_cp_compute_enable()
H A Dgfx_v8_0.c4305 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable()
4307 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
H A Dgfx_v10_0.c341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
6579 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v10_0_cp_compute_enable()
6597 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, in gfx_v10_0_cp_compute_enable()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h319 #define mmCP_MEC_CNTL 0x208d macro
H A Dgfx_7_2_d.h322 #define mmCP_MEC_CNTL 0x208d macro
H A Dgfx_8_0_d.h357 #define mmCP_MEC_CNTL 0x208d macro
H A Dgfx_8_1_d.h357 #define mmCP_MEC_CNTL 0x208d macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h135 #define mmCP_MEC_CNTL … macro
H A Dgc_9_1_offset.h135 #define mmCP_MEC_CNTL … macro
H A Dgc_9_2_1_offset.h137 #define mmCP_MEC_CNTL … macro
H A Dgc_10_1_0_offset.h2143 #define mmCP_MEC_CNTL … macro
H A Dgc_10_3_0_offset.h2280 #define mmCP_MEC_CNTL … macro