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Searched refs:mmCP_INT_CNTL_RING0 (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2232 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_enable_gui_idle_interrupt()
2242 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v6_0_enable_gui_idle_interrupt()
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3216 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state()
3218 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state()
3274 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_priv_reg_fault_state()
3276 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3281 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_reg_fault_state()
3301 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_priv_inst_fault_state()
[all …]
H A Dgfx_v7_0.c3062 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3070 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v7_0_enable_gui_idle_interrupt()
4631 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4633 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4636 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4638 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
4705 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4707 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4712 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
4732 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state()
[all …]
H A Dgfx_v8_0.c3868 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v8_0_enable_gui_idle_interrupt()
3875 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v8_0_enable_gui_idle_interrupt()
H A Dgfx_v9_0.c2733 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v9_0_enable_gui_idle_interrupt()
2741 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); in gfx_v9_0_enable_gui_idle_interrupt()
H A Dgfx_v10_0.c5347 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_get_cpg_int_cntl()
9040 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_set_gfx_eop_interrupt_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h438 #define mmCP_INT_CNTL_RING0 0x306A macro
H A Dgfx_7_0_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_7_2_d.h222 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_8_0_d.h246 #define mmCP_INT_CNTL_RING0 0x306a macro
H A Dgfx_8_1_d.h247 #define mmCP_INT_CNTL_RING0 0x306a macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2468 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_9_1_offset.h2745 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_9_2_1_offset.h2683 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_10_1_0_offset.h4807 #define mmCP_INT_CNTL_RING0 … macro
H A Dgc_10_3_0_offset.h4460 #define mmCP_INT_CNTL_RING0 … macro