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Searched refs:mmCP_HQD_EOP_CONTROL (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v8.c186 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) in kgd_hqd_load()
H A Dgfx_v9_0.c263 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
3552 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in gfx_v9_0_mqd_init()
3668 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, in gfx_v9_0_kiq_init_register()
H A Dgfx_v8_0.c4444 tmp = RREG32(mmCP_HQD_EOP_CONTROL); in gfx_v8_0_mqd_init()
4581 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++) in gfx_v8_0_mqd_commit()
H A Dgfx_v10_0.c405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
6888 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); in gfx_v10_0_compute_mqd_init()
7025 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, in gfx_v10_0_kiq_init_register()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h672 #define mmCP_HQD_EOP_CONTROL 0x326c macro
H A Dgfx_8_1_d.h672 #define mmCP_HQD_EOP_CONTROL 0x326c macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2901 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_9_1_offset.h3129 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_9_2_1_offset.h3085 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_10_1_0_offset.h5385 #define mmCP_HQD_EOP_CONTROL … macro
H A Dgc_10_3_0_offset.h5018 #define mmCP_HQD_EOP_CONTROL … macro