Home
last modified time | relevance | path

Searched refs:mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c8186 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()
8194 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h9942 #define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX … macro