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Searched refs:misaligned (Results 1 – 25 of 34) sorted by relevance

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/linux-6.15/drivers/dma/
H A Dpxa_dma.c90 bool misaligned; member
113 bool misaligned; member
460 phy, phy->idx, misaligned); in phy_enable()
469 if (misaligned) in phy_enable()
512 phy_enable(chan->phy, chan->misaligned); in pxad_launch_chan()
571 to_pxad_sw_desc(vd)->misaligned) in pxad_try_hotchain()
652 chan->misaligned = in pxad_chan_handler()
809 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) in pxad_tx_submit()
818 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; in pxad_tx_submit()
944 sw_desc->misaligned = true; in pxad_prep_memcpy()
[all …]
/linux-6.15/arch/nios2/kernel/
H A DMakefile26 obj-$(CONFIG_NIOS2_ALIGNMENT_TRAP) += misaligned.o
/linux-6.15/arch/alpha/lib/
H A Dev67-strlen.S29 ldq_u $1, 0($16) # L : load first quadword ($16 may be misaligned)
H A Dev67-strcat.S35 ldq_u $1, 0($16) # L : load first quadword (a0 may be misaligned)
H A Dstrcat.S23 ldq_u $1, 0($16) # load first quadword (a0 may be misaligned)
H A Dstrlen.S25 ldq_u $1, 0($16) # load first quadword ($16 may be misaligned)
H A Dstrncat.S28 ldq_u $1, 0($16) # load first quadword ($16 may be misaligned)
H A Dev6-clear_user.S57 and $1, 7, $2 # .. .. E .. : number of misaligned bytes in tail
69 mskql $5, $16, $5 # .. U .. .. : take care of misaligned head
H A Dev67-strncat.S37 ldq_u $1, 0($16) # L : load first quadword ($16 may be misaligned)
H A Dev6-memcpy.S39 bne $1, $misaligned # U : Nope - gotta do this the slow way
181 $misaligned:
H A Dclear_user.S81 mskql $5, $16, $5 # e0 : take care of misaligned head
/linux-6.15/Documentation/arch/riscv/
H A Dhwprobe.rst279 the performance of misaligned scalar native word accesses on the selected set
283 misaligned scalar accesses is unknown.
299 accesses are not supported at all and will generate a misaligned address
311 performance of misaligned vector accesses on the selected set of processors.
313 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
316 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
320 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
324 not supported at all and will generate a misaligned address fault.
/linux-6.15/drivers/staging/gpib/
H A DTODO6 - sometimes they are misaligned
/linux-6.15/Documentation/arch/arm/
H A Dmem_alignment.rst5 Too many problems popped up because of unnoticed misaligned memory access in
16 alignment trap can fixup misaligned access for the exception cases, but at
/linux-6.15/arch/m68k/ifpsp060/
H A DCHANGES86 bit 27 = 1 (misaligned bit)
108 bit 27 = 0 (misaligned bit)
H A Disp.doc46 cas (w/ a misaligned effective address)
174 The instructions "cas2" and "cas" (when used with a misaligned effective
/linux-6.15/scripts/coccinelle/misc/
H A Dcond_no_effect.cocci26 // /* misaligned */
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_guc_capture.c1008 int misaligned; in guc_capture_log_remove_bytes() local
1011 misaligned = avail % sizeof(u32); in guc_capture_log_remove_bytes()
1022 copy_size = avail < bytes_needed ? avail - misaligned : bytes_needed; in guc_capture_log_remove_bytes()
1029 if (misaligned) in guc_capture_log_remove_bytes()
/linux-6.15/Documentation/core-api/
H A Dprintk-index.rst50 <5> block/blk-settings.c:661 disk_stack_limits "%s: Warning: Device %s is misaligned\n"
/linux-6.15/lib/
H A DKconfig.ubsan152 bool "Perform checking for misaligned pointer usage"
/linux-6.15/arch/arm/kernel/
H A Dhead.S589 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r0.
/linux-6.15/Documentation/sphinx/
H A Dkerneldoc-preamble.sty178 % For CJK ascii-art alignment (still misaligned for Hangul)
/linux-6.15/tools/perf/Documentation/
H A Dperf-arm-spe.txt164 bit 11 - misaligned access
/linux-6.15/arch/riscv/
H A DKconfig904 Embed support for detecting and emulating misaligned
912 Embed support for emulating misaligned loads and stores.
919 Enable detecting support for vector misaligned loads and stores.
/linux-6.15/arch/arc/
H A DKconfig510 This enables misaligned 16 & 32 bit memory access from user space.

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