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Searched refs:mipi_dsi_dcs_write_seq_multi (Results 1 – 25 of 36) sorted by relevance

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/linux-6.15/drivers/gpu/drm/panel/
H A Dpanel-boe-tv101wum-nl6.c64 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); in nt36523_enable_reload_cmds()
73 mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0xd9); in boe_tv110c9m_init()
74 mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x78); in boe_tv110c9m_init()
75 mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x5a); in boe_tv110c9m_init()
76 mipi_dsi_dcs_write_seq_multi(&ctx, 0x0d, 0x63); in boe_tv110c9m_init()
77 mipi_dsi_dcs_write_seq_multi(&ctx, 0x0e, 0x91); in boe_tv110c9m_init()
78 mipi_dsi_dcs_write_seq_multi(&ctx, 0x0f, 0x73); in boe_tv110c9m_init()
428 mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); in boe_tv110c9m_init()
432 mipi_dsi_dcs_write_seq_multi(&ctx, 0x29); in boe_tv110c9m_init()
827 mipi_dsi_dcs_write_seq_multi(&ctx, 0x11); in inx_hj110iz_init()
[all …]
H A Dpanel-jadard-jd9365da-h3.c55 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93); in jadard_enable_standard_cmds()
56 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65); in jadard_enable_standard_cmds()
57 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8); in jadard_enable_standard_cmds()
58 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03); in jadard_enable_standard_cmds()
194 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); in radxa_display_8hd_ad002_init_cmds()
195 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); in radxa_display_8hd_ad002_init_cmds()
196 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); in radxa_display_8hd_ad002_init_cmds()
197 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); in radxa_display_8hd_ad002_init_cmds()
198 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); in radxa_display_8hd_ad002_init_cmds()
199 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); in radxa_display_8hd_ad002_init_cmds()
[all …]
H A Dpanel-ilitek-ili9882t.c71 mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x42); in starry_ili9882t_init()
72 mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x11); in starry_ili9882t_init()
73 mipi_dsi_dcs_write_seq_multi(&ctx, 0x02, 0x00); in starry_ili9882t_init()
74 mipi_dsi_dcs_write_seq_multi(&ctx, 0x03, 0x00); in starry_ili9882t_init()
76 mipi_dsi_dcs_write_seq_multi(&ctx, 0x04, 0x01); in starry_ili9882t_init()
77 mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0x11); in starry_ili9882t_init()
78 mipi_dsi_dcs_write_seq_multi(&ctx, 0x06, 0x00); in starry_ili9882t_init()
79 mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x00); in starry_ili9882t_init()
81 mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x80); in starry_ili9882t_init()
82 mipi_dsi_dcs_write_seq_multi(&ctx, 0x09, 0x81); in starry_ili9882t_init()
[all …]
H A Dpanel-ilitek-ili9806e.c232 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x18); in com35h3p70ulc_init()
233 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); in com35h3p70ulc_init()
235 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03); in com35h3p70ulc_init()
236 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); in com35h3p70ulc_init()
237 mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x0d); in com35h3p70ulc_init()
238 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x08); in com35h3p70ulc_init()
239 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x08); in com35h3p70ulc_init()
240 mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x09); in com35h3p70ulc_init()
242 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x30); in com35h3p70ulc_init()
243 mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44); in com35h3p70ulc_init()
[all …]
H A Dpanel-novatek-nt36672e.c54 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); in nt36672e_enable_reload_cmds()
66 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00); in nt36672e_1080x2408_60hz_init()
67 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); in nt36672e_1080x2408_60hz_init()
74 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66); in nt36672e_1080x2408_60hz_init()
75 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40); in nt36672e_1080x2408_60hz_init()
76 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38); in nt36672e_1080x2408_60hz_init()
77 mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x83); in nt36672e_1080x2408_60hz_init()
78 mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x91); in nt36672e_1080x2408_60hz_init()
79 mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0xd1); in nt36672e_1080x2408_60hz_init()
80 mipi_dsi_dcs_write_seq_multi(ctx, 0x96, 0xd1); in nt36672e_1080x2408_60hz_init()
[all …]
H A Dpanel-himax-hx83102.c108 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); in starry_himax83102_j02_init()
109 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); in starry_himax83102_j02_init()
110 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); in starry_himax83102_j02_init()
117 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); in starry_himax83102_j02_init()
124 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); in starry_himax83102_j02_init()
157 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); in starry_himax83102_j02_init()
165 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); in starry_himax83102_j02_init()
171 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); in starry_himax83102_j02_init()
179 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); in starry_himax83102_j02_init()
181 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); in starry_himax83102_j02_init()
[all …]
H A Dpanel-newvision-nv3051d.c57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); in panel_nv3051d_init_sequence()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); in panel_nv3051d_init_sequence()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x01); in panel_nv3051d_init_sequence()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x00); in panel_nv3051d_init_sequence()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40); in panel_nv3051d_init_sequence()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x00); in panel_nv3051d_init_sequence()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x03); in panel_nv3051d_init_sequence()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x12); in panel_nv3051d_init_sequence()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x1E); in panel_nv3051d_init_sequence()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x28); in panel_nv3051d_init_sequence()
[all …]
H A Dpanel-visionox-rm692e5.c61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x40); in visionox_rm692e5_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x07); in visionox_rm692e5_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd2); in visionox_rm692e5_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x11); in visionox_rm692e5_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x30); in visionox_rm692e5_on()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x60); in visionox_rm692e5_on()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x38); in visionox_rm692e5_on()
72 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x00); in visionox_rm692e5_on()
73 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x14); in visionox_rm692e5_on()
74 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x02); in visionox_rm692e5_on()
[all …]
H A Dpanel-sitronix-st7703.c167 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, in xbd599_init_sequence()
186 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, in xbd599_init_sequence()
197 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, in xbd599_init_sequence()
221 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, in xbd599_init_sequence()
231 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, in xbd599_init_sequence()
253 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, in xbd599_init_sequence()
271 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, in xbd599_init_sequence()
275 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, in xbd599_init_sequence()
283 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, in xbd599_init_sequence()
294 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, in xbd599_init_sequence()
[all …]
H A Dpanel-himax-hx83112a.c66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETPOWER1, in hx83112a_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDISP, in hx83112a_on()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, in hx83112a_on()
77 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETDRV, in hx83112a_on()
113 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTCON, in hx83112a_on()
117 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0, in hx83112a_on()
126 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP0, in hx83112a_on()
129 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETGIP1, in hx83112a_on()
162 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTP1, in hx83112a_on()
167 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83112A_SETTP1, in hx83112a_on()
[all …]
H A Dpanel-boe-th101mb31ig002-28a.c65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); in boe_th101mb31ig002_enable()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); in boe_th101mb31ig002_enable()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); in boe_th101mb31ig002_enable()
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); in boe_th101mb31ig002_enable()
96 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc6, 0x2a, 0x2a); in boe_th101mb31ig002_enable()
98 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); in boe_th101mb31ig002_enable()
107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00); in boe_th101mb31ig002_enable()
124 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); in starry_er88577_init_cmd()
125 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); in starry_er88577_init_cmd()
155 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); in starry_er88577_init_cmd()
[all …]
H A Dpanel-leadtek-ltk050h3146w.c256 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd2, 0x88); in ltk050h3148w_init_sequence()
286 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xcc, 0x0b); in ltk050h3148w_init_sequence()
287 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc0, 0x1f, 0x31); in ltk050h3148w_init_sequence()
289 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x01); in ltk050h3148w_init_sequence()
290 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xb1, 0x00); in ltk050h3148w_init_sequence()
291 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xbd, 0x00); in ltk050h3148w_init_sequence()
292 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc6, 0xef); in ltk050h3148w_init_sequence()
293 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xd4, 0x02); in ltk050h3148w_init_sequence()
368 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xde, 0x02); in ltk050h3146w_init_sequence()
371 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xc1, 0x11); in ltk050h3146w_init_sequence()
[all …]
H A Dpanel-visionox-vtdr6130.c55 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, in visionox_vtdr6130_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x09); in visionox_vtdr6130_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x01); in visionox_vtdr6130_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); in visionox_vtdr6130_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01); in visionox_vtdr6130_on()
104 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x14); in visionox_vtdr6130_on()
107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); in visionox_vtdr6130_on()
108 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x0f); in visionox_vtdr6130_on()
111 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf9, 0x00); in visionox_vtdr6130_on()
[all …]
H A Dpanel-samsung-ams639rq08.c61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a); in ams639rq08_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0x5a, 0x5a); in ams639rq08_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_FF, 0x10); in ams639rq08_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0xa5, 0xa5); in ams639rq08_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD2, 0xa5, 0xa5); in ams639rq08_on()
75 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD1, 0x5a, 0x5a); in ams639rq08_on()
84 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_UNKNOWN_B7, 0x10); in ams639rq08_on()
98 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe9, 0x11, 0x55, in ams639rq08_on()
104 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, in ams639rq08_on()
107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, in ams639rq08_on()
[all …]
H A Dpanel-samsung-s6e3ha8.c40 mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x5a, 0x5a)
81 mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13); in s6e3ha8_amb577px01_wqhd_on()
86 mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x13); in s6e3ha8_amb577px01_wqhd_on()
91 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x07); in s6e3ha8_amb577px01_wqhd_on()
94 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x0b); in s6e3ha8_amb577px01_wqhd_on()
96 mipi_dsi_dcs_write_seq_multi(&ctx, 0xf2, 0x30); in s6e3ha8_amb577px01_wqhd_on()
115 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, in s6e3ha8_amb577px01_wqhd_on()
121 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x03); in s6e3ha8_amb577px01_wqhd_on()
122 mipi_dsi_dcs_write_seq_multi(&ctx, 0xf6, 0x43); in s6e3ha8_amb577px01_wqhd_on()
127 mipi_dsi_dcs_write_seq_multi(&ctx, 0xca, in s6e3ha8_amb577px01_wqhd_on()
[all …]
H A Dpanel-visionox-r66451.c49 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x00); in visionox_r66451_on()
50 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, in visionox_r66451_on()
53 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, in visionox_r66451_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x80); in visionox_r66451_on()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xde, in visionox_r66451_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, in visionox_r66451_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcf, in visionox_r66451_on()
72 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3, in visionox_r66451_on()
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd7, in visionox_r66451_on()
80 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd8, in visionox_r66451_on()
[all …]
H A Dpanel-lincolntech-lcd197.c52 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0xff, 0x83, 0x99); in lincoln_lcd197_panel_prepare()
53 mipi_dsi_dcs_write_seq_multi(&ctx, 0xd2, 0x55); in lincoln_lcd197_panel_prepare()
54 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x02, 0x04, 0x70, 0x90, 0x01, in lincoln_lcd197_panel_prepare()
57 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x00, 0x80, 0x80, 0xae, 0x0a, in lincoln_lcd197_panel_prepare()
81 mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x01); in lincoln_lcd197_panel_prepare()
86 mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x02); in lincoln_lcd197_panel_prepare()
98 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x92, 0x92); in lincoln_lcd197_panel_prepare()
99 mipi_dsi_dcs_write_seq_multi(&ctx, 0xcc, 0x00); in lincoln_lcd197_panel_prepare()
100 mipi_dsi_dcs_write_seq_multi(&ctx, 0xbf, 0x40, 0x41, 0x50, 0x49); in lincoln_lcd197_panel_prepare()
101 mipi_dsi_dcs_write_seq_multi(&ctx, 0xc6, 0xff, 0xf9); in lincoln_lcd197_panel_prepare()
[all …]
H A Dpanel-xinpeng-xpp055c272.c69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
76 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
79 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
82 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
83 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
84 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
86 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETEQ, in xpp055c272_init_sequence()
89 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETPOWER, in xpp055c272_init_sequence()
98 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP1, in xpp055c272_init_sequence()
107 mipi_dsi_dcs_write_seq_multi(dsi_ctx, XPP055C272_CMD_SETGIP2, in xpp055c272_init_sequence()
[all …]
H A Dpanel-samsung-s6e88a0-ams427ap24.c508 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // level 1 key on in s6e88a0_ams427ap24_set_brightness()
510 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x00); // acl off in s6e88a0_ams427ap24_set_brightness()
513 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma update in s6e88a0_ams427ap24_set_brightness()
538 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // level 1 key on in s6e88a0_ams427ap24_on()
539 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfc, 0x5a, 0x5a); // level 2 key on in s6e88a0_ams427ap24_on()
541 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfd, 0x11); // src latch set 1 in s6e88a0_ams427ap24_on()
543 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfd, 0x18); // src latch set 2 in s6e88a0_ams427ap24_on()
544 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0x02); // avdd set 1 in s6e88a0_ams427ap24_on()
545 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x30); // avdd set 2 in s6e88a0_ams427ap24_on()
552 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf2, 0x03, 0x0d); // unknown in s6e88a0_ams427ap24_on()
[all …]
H A Dpanel-elida-kd35t133.c59 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
62 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
66 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
68 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
69 mipi_dsi_dcs_write_seq_multi(dsi_ctx, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
70 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
71 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
73 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_DISPLAYFUNCTIONCTRL, in kd35t133_init_sequence()
75 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_SETIMAGEFUNCTION, 0x00); in kd35t133_init_sequence()
76 mipi_dsi_dcs_write_seq_multi(dsi_ctx, KD35T133_CMD_ADJUSTCONTROL3, in kd35t133_init_sequence()
[all …]
H A Dpanel-samsung-ams581vf01.c64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0x5a, 0x5a); /* Unlock */ in ams581vf01_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xeb, 0x17, in ams581vf01_on()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0xa5, 0xa5); /* Lock */ in ams581vf01_on()
76 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in ams581vf01_on()
79 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0x5a, 0x5a); /* Unlock */ in ams581vf01_on()
80 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x09); in ams581vf01_on()
81 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe8, 0x11, 0x30); in ams581vf01_on()
82 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PASSWD, 0xa5, 0xa5); /* Lock */ in ams581vf01_on()
103 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_ACCESS_PROT_OFF, 0x05); in ams581vf01_off()
104 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x01); in ams581vf01_off()
[all …]
H A Dpanel-lg-sw43408.c66 mipi_dsi_dcs_write_seq_multi(&ctx, MIPI_DCS_SET_GAMMA_CURVE, 0x02); in sw43408_program()
70 mipi_dsi_dcs_write_seq_multi(&ctx, 0x53, 0x0c, 0x30); in sw43408_program()
71 mipi_dsi_dcs_write_seq_multi(&ctx, 0x55, 0x00, 0x70, 0xdf, 0x00, 0x70, 0xdf); in sw43408_program()
72 mipi_dsi_dcs_write_seq_multi(&ctx, 0xf7, 0x01, 0x49, 0x0c); in sw43408_program()
80 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0xac); in sw43408_program()
81 mipi_dsi_dcs_write_seq_multi(&ctx, 0xe5, in sw43408_program()
83 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, in sw43408_program()
91 mipi_dsi_dcs_write_seq_multi(&ctx, 0xcd, in sw43408_program()
95 mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x80, 0x5c, 0x07, 0x03, 0x28); in sw43408_program()
96 mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x02, 0x02, 0x0f); in sw43408_program()
[all …]
H A Dpanel-boe-tv101wum-ll2.c56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e); in boe_tv101wum_ll2_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22, in boe_tv101wum_ll2_on()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23); in boe_tv101wum_ll2_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00); in boe_tv101wum_ll2_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00); in boe_tv101wum_ll2_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19); in boe_tv101wum_ll2_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38); in boe_tv101wum_ll2_on()
91 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5a); in boe_tv101wum_ll2_off()
92 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5a); in boe_tv101wum_ll2_off()
H A Dpanel-raydium-rm69380.c55 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd4); in rm69380_on()
56 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x80); in rm69380_on()
57 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0xd0); in rm69380_on()
58 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x00); in rm69380_on()
59 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x26); in rm69380_on()
60 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f); in rm69380_on()
61 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1a); in rm69380_on()
62 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x00); in rm69380_on()
63 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x28); in rm69380_on()
64 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x08); in rm69380_on()
H A Dpanel-samsung-s6e88a0-ams452ef01.c46 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
47 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
53 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, in s6e88a0_ams452ef01_on()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()

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