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Searched refs:mipi_dsi_dcs_write_seq (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt36523.c490 mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20); in j606f_boe_init_sequence()
491 mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01); in j606f_boe_init_sequence()
492 mipi_dsi_dcs_write_seq(dsi, 0x05, 0xd9); in j606f_boe_init_sequence()
493 mipi_dsi_dcs_write_seq(dsi, 0x07, 0x78); in j606f_boe_init_sequence()
494 mipi_dsi_dcs_write_seq(dsi, 0x08, 0x5a); in j606f_boe_init_sequence()
495 mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x63); in j606f_boe_init_sequence()
496 mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x91); in j606f_boe_init_sequence()
497 mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x73); in j606f_boe_init_sequence()
498 mipi_dsi_dcs_write_seq(dsi, 0x95, 0xeb); in j606f_boe_init_sequence()
499 mipi_dsi_dcs_write_seq(dsi, 0x96, 0xeb); in j606f_boe_init_sequence()
[all …]
H A Dpanel-himax-hx8394.c96 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
100 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
104 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
108 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
112 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
118 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
125 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
133 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
159 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, in hsd060bhw4_init_sequence()
213 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in powkiddy_x55_init_sequence()
[all …]
H A Dpanel-samsung-s6d7aa0.c70 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5); in s6d7aa0_lock()
71 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5); in s6d7aa0_lock()
73 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a); in s6d7aa0_lock()
75 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a); in s6d7aa0_lock()
76 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a); in s6d7aa0_lock()
249 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x10); in s6d7aa0_lsl080al02_init()
350 mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x51); in s6d7aa0_lsl080al03_init()
357 mipi_dsi_dcs_write_seq(dsi, 0xcd, in s6d7aa0_lsl080al03_init()
360 mipi_dsi_dcs_write_seq(dsi, 0xce, in s6d7aa0_lsl080al03_init()
363 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x03); in s6d7aa0_lsl080al03_init()
[all …]
H A Dpanel-boe-bf060y8m-aj0.c61 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
62 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0x4c); in boe_bf060y8m_aj0_on()
63 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x10); in boe_bf060y8m_aj0_on()
64 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, DCS_ALLOW_HBM_RANGE); in boe_bf060y8m_aj0_on()
65 mipi_dsi_dcs_write_seq(dsi, 0xf8, in boe_bf060y8m_aj0_on()
75 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
76 mipi_dsi_dcs_write_seq(dsi, 0xc0, in boe_bf060y8m_aj0_on()
79 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x00, 0x00, 0x1f, 0x1f, in boe_bf060y8m_aj0_on()
82 mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x20, 0x04, 0x10, 0x12, 0x92, in boe_bf060y8m_aj0_on()
85 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x01, 0x2c, 0x00, 0x77, 0x3e); in boe_bf060y8m_aj0_on()
H A Dpanel-samsung-sofef00.c59 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
67 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
68 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
69 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
73 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
/linux-6.15/include/drm/
H A Ddrm_mipi_dsi.h432 #define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) \ macro
/linux-6.15/Documentation/gpu/
H A Dtodo.rst502 The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are