Searched refs:min_ddb (Results 1 – 2 of 2) sorted by relevance
| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | skl_watermark.c | 805 u16 *min_ddb, u16 *interim_ddb) in skl_ddb_get_hw_plane_state() argument
823 *min_ddb = REG_FIELD_GET(PLANE_MIN_DBUF_BLOCKS_MASK, val); in skl_ddb_get_hw_plane_state()
837 u16 *min_ddb, u16 *interim_ddb) in skl_pipe_ddb_get_hw_state() argument
856 &min_ddb[plane_id], in skl_pipe_ddb_get_hw_state()
1639 u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_crtc_allocate_plane_ddb() local
1660 *min_ddb = wm->wm[0].min_ddb_alloc; in skl_crtc_allocate_plane_ddb()
3188 u16 *min_ddb = in skl_wm_get_hw_state() local
3198 min_ddb, interim_ddb); in skl_wm_get_hw_state()
3906 u16 min_ddb[I915_MAX_PLANES]; in intel_wm_state_verify() member
3924 skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); in intel_wm_state_verify()
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| H A D | skl_universal_plane.c | 793 static u32 xe3_plane_min_ddb_reg_val(const u16 *min_ddb, in xe3_plane_min_ddb_reg_val() argument
798 if (*min_ddb) in xe3_plane_min_ddb_reg_val()
799 val |= PLANE_MIN_DBUF_BLOCKS(*min_ddb); in xe3_plane_min_ddb_reg_val()
838 const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_write_plane_wm() local
868 xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb)); in skl_write_plane_wm()
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