Searched refs:mg_pll_div1 (Results 1 – 2 of 2) sorted by relevance
221 u32 mg_pll_div1; member
3118 hw_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()3139 hw_state->mg_pll_div1 = in icl_calc_mg_pll_state()3226 m1 = hw_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()3583 hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()3657 hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()3658 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()3828 intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()3883 val |= hw_state->mg_pll_div1; in dkl_pll_write()4104 hw_state->mg_pll_div1, in icl_dump_hw_state()4126 a->mg_pll_div1 == b->mg_pll_div1 && in icl_compare_hw_state()