Searched refs:mfdcr (Results 1 – 9 of 9) sorted by relevance
152 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); in mcue_handler()160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); in mcue_handler()162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); in mcue_handler()164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); in mcue_handler()166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); in mcue_handler()178 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); in mcue_handler()180 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); in mcue_handler()182 mfdcr(DCRN_PLB6MCIF_BESR0)); in mcue_handler()184 mfdcr(DCRN_PLB6MCIF_BEARL)); in mcue_handler()186 mfdcr(DCRN_PLB6MCIF_BEARH)); in mcue_handler()[all …]
37 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()40 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()45 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()127 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()129 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()131 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()138 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()147 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()154 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & in ppc4xx_l2c_probe()159 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & in ppc4xx_l2c_probe()[all …]
64 er = mfdcr(uic->dcrbase + UIC_ER); in uic_unmask_irq()78 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_irq()104 er = mfdcr(uic->dcrbase + UIC_ER); in uic_mask_ack_irq()152 tr = mfdcr(uic->dcrbase + UIC_TR); in uic_set_irq_type()153 pr = mfdcr(uic->dcrbase + UIC_PR); in uic_set_irq_type()211 msr = mfdcr(uic->dcrbase + UIC_MSR); in uic_irq_cascade()327 msr = mfdcr(primary_uic->dcrbase + UIC_MSR); in uic_get_irq()
256 data = mfdcr(DCRN_CMU_DATA); \268 data = mfdcr(DCRN_L2CDCRDI); \
106 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); in ibm440spe_fixup_memsize()109 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); in ibm440spe_fixup_memsize()112 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); in ibm440spe_fixup_memsize()115 banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); in ibm440spe_fixup_memsize()284 while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) in ibm4xx_quiesce_eth()300 bxcr = mfdcr(DCRN_EBC0_CFGDATA); in ibm4xx_fixup_ebc_ranges()320 u32 sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_fixup_clocks()321 u32 cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_fixup_clocks()
5 #define mfdcr(rn) \ macro30 mfdcr(DCRN_SDRAM0_CFGDATA); })172 mfdcr(DCRN_SDR0_CONFIG_DATA); })190 mfdcr(DCRN_CPR0_CFGDATA); })
35 mfdcr r3,0; blr41 mfdcr r3,dcr; blr
29 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)53 #define mfdcr(rn) \ macro
63 mfdcr r3,DCRN_PLB4A0_ACR