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Searched refs:mec_int_cntl_reg (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3021 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state() local
3057 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3063 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3100 u32 mec_int_cntl_reg, mec_int_cntl; in gfx_v9_4_3_set_priv_reg_fault_state() local
3116 if (mec_int_cntl_reg) { in gfx_v9_4_3_set_priv_reg_fault_state()
3117 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); in gfx_v9_4_3_set_priv_reg_fault_state()
3122 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); in gfx_v9_4_3_set_priv_reg_fault_state()
3140 u32 mec_int_cntl_reg, mec_int_cntl; in gfx_v9_4_3_set_bad_op_fault_state() local
3156 if (mec_int_cntl_reg) { in gfx_v9_4_3_set_bad_op_fault_state()
3157 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); in gfx_v9_4_3_set_bad_op_fault_state()
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H A Dgfx_v7_0.c4649 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v7_0_set_compute_eop_interrupt_state() local
4660 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4663 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4666 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4669 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
4682 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4684 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
4687 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4689 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6419 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v8_0_set_compute_eop_interrupt_state() local
6430 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6433 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6436 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6439 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
6452 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6454 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
6457 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v8_0_set_compute_eop_interrupt_state()
6459 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v8_0_set_compute_eop_interrupt_state()
H A Dgfx_v12_0.c4671 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v12_0_set_compute_eop_interrupt_state() local
4682 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4685 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v12_0_set_compute_eop_interrupt_state()
4698 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4703 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
4706 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v12_0_set_compute_eop_interrupt_state()
4711 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v12_0_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c6212 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v11_0_set_compute_eop_interrupt_state() local
6223 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6226 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6229 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6232 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6245 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6250 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
6253 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v11_0_set_compute_eop_interrupt_state()
6258 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c5972 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v9_0_set_compute_eop_interrupt_state() local
5983 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5986 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5989 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
5992 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6005 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6008 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
6011 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v9_0_set_compute_eop_interrupt_state()
6014 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c9076 u32 mec_int_cntl, mec_int_cntl_reg; in gfx_v10_0_set_compute_eop_interrupt_state() local
9087 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9090 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9093 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9096 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
9109 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9112 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()
9115 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); in gfx_v10_0_set_compute_eop_interrupt_state()
9118 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); in gfx_v10_0_set_compute_eop_interrupt_state()