Searched refs:mec_hdr (Results 1 – 7 of 7) sorted by relevance
2812 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v11_0_config_mec_cache_rs64()2813 mec_hdr->ucode_start_addr_hi << 30); in gfx_v11_0_config_mec_cache_rs64()2815 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v11_0_config_mec_cache_rs64()2927 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v11_0_config_gfx_rs64()2928 mec_hdr->ucode_start_addr_hi << 30); in gfx_v11_0_config_gfx_rs64()2930 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v11_0_config_gfx_rs64()3818 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v11_0_cp_compute_load_microcode()3849 le32_to_cpu(mec_hdr->data_offset_bytes)); in gfx_v11_0_cp_compute_load_microcode_rs64()3906 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v11_0_cp_compute_load_microcode_rs64()3907 mec_hdr->ucode_start_addr_hi << 30); in gfx_v11_0_cp_compute_load_microcode_rs64()[all …]
620 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_4_3_mec_init() local658 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_4_3_mec_init()662 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_4_3_mec_init()663 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v9_4_3_mec_init()665 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v9_4_3_mec_init()1706 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_4_3_xcc_cp_compute_load_microcode() local1719 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1723 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1740 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1741 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v9_4_3_xcc_cp_compute_load_microcode()[all …]
2032 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v12_0_config_gfx_rs64() local2035 mec_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2090 mec_hdr->ucode_start_addr_lo >> 2 | in gfx_v12_0_config_gfx_rs64()2091 mec_hdr->ucode_start_addr_hi << 30); in gfx_v12_0_config_gfx_rs64()2093 mec_hdr->ucode_start_addr_hi >> 2); in gfx_v12_0_config_gfx_rs64()2731 const struct gfx_firmware_header_v2_0 *mec_hdr; in gfx_v12_0_cp_compute_load_microcode_rs64() local2744 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v12_0_cp_compute_load_microcode_rs64()2747 le32_to_cpu(mec_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_compute_load_microcode_rs64()2748 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); in gfx_v12_0_cp_compute_load_microcode_rs64()2751 le32_to_cpu(mec_hdr->data_offset_bytes)); in gfx_v12_0_cp_compute_load_microcode_rs64()[all …]
1877 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_0_mec_init() local1903 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v9_0_mec_init()1907 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_mec_init()1908 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v9_0_mec_init()1910 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v9_0_mec_init()3455 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v9_0_cp_compute_load_microcode() local3466 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v9_0_cp_compute_load_microcode()3470 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_cp_compute_load_microcode()3483 mec_hdr->jt_offset); in gfx_v9_0_cp_compute_load_microcode()3484 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v9_0_cp_compute_load_microcode()[all …]
2655 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v7_0_cp_compute_load_microcode() local2662 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()2663 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v7_0_cp_compute_load_microcode()2664 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()2666 mec_hdr->ucode_feature_version); in gfx_v7_0_cp_compute_load_microcode()2673 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_cp_compute_load_microcode()2674 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; in gfx_v7_0_cp_compute_load_microcode()
4422 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; in gfx_v10_0_mec_init() local4449 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()4452 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_mec_init()4453 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); in gfx_v10_0_mec_init()4455 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, in gfx_v10_0_mec_init()6609 const struct gfx_firmware_header_v1_0 *mec_hdr; in gfx_v10_0_cp_compute_load_microcode() local6620 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()6621 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); in gfx_v10_0_cp_compute_load_microcode()6625 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_compute_load_microcode()6663 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v10_0_cp_compute_load_microcode()[all …]
4256 const struct gfx_firmware_header_v1_0 *mec_hdr = in cik_cp_compute_load_microcode() local4261 radeon_ucode_print_gfx_hdr(&mec_hdr->header); in cik_cp_compute_load_microcode()4265 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); in cik_cp_compute_load_microcode()4266 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; in cik_cp_compute_load_microcode()4270 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()