Searched refs:me_hdr (Results 1 – 8 of 8) sorted by relevance
2721 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_me_cache_rs64()2722 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_me_cache_rs64()2724 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_me_cache_rs64()2905 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_config_gfx_rs64()2906 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_config_gfx_rs64()2908 me_hdr->ucode_start_addr_hi>>2); in gfx_v11_0_config_gfx_rs64()3306 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_me_microcode()3335 le32_to_cpu(me_hdr->data_offset_bytes)); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()3428 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v11_0_cp_gfx_load_me_microcode_rs64()3429 (me_hdr->ucode_start_addr_lo >> 2) ); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()[all …]
2031 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_config_gfx_rs64() local2037 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_config_gfx_rs64()2068 (me_hdr->ucode_start_addr_hi << 30) | in gfx_v12_0_config_gfx_rs64()2069 (me_hdr->ucode_start_addr_lo >> 2)); in gfx_v12_0_config_gfx_rs64()2071 me_hdr->ucode_start_addr_hi>>2); in gfx_v12_0_config_gfx_rs64()2419 const struct gfx_firmware_header_v2_0 *me_hdr; in gfx_v12_0_cp_gfx_load_me_microcode_rs64() local2425 me_hdr = (const struct gfx_firmware_header_v2_0 *) in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2428 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2432 le32_to_cpu(me_hdr->ucode_offset_bytes)); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()2436 le32_to_cpu(me_hdr->data_offset_bytes)); in gfx_v12_0_cp_gfx_load_me_microcode_rs64()[all …]
2392 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v7_0_cp_gfx_load_microcode() local2401 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()2405 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v7_0_cp_gfx_load_microcode()2408 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()2409 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()2438 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_cp_gfx_load_microcode()2439 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v7_0_cp_gfx_load_microcode()
1947 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v6_0_cp_gfx_load_microcode() local1957 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_cp_gfx_load_microcode()1961 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v6_0_cp_gfx_load_microcode()1983 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v6_0_cp_gfx_load_microcode()1984 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v6_0_cp_gfx_load_microcode()
6221 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v10_0_cp_gfx_load_me_microcode() local6227 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v10_0_cp_gfx_load_me_microcode()6230 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v10_0_cp_gfx_load_me_microcode()6233 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_cp_gfx_load_me_microcode()6234 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); in gfx_v10_0_cp_gfx_load_me_microcode()6236 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, in gfx_v10_0_cp_gfx_load_me_microcode()6286 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v10_0_cp_gfx_load_me_microcode()6288 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_me_microcode()
3241 const struct gfx_firmware_header_v1_0 *me_hdr; in gfx_v9_0_cp_gfx_load_microcode() local3252 me_hdr = (const struct gfx_firmware_header_v1_0 *) in gfx_v9_0_cp_gfx_load_microcode()3257 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); in gfx_v9_0_cp_gfx_load_microcode()3284 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in gfx_v9_0_cp_gfx_load_microcode()3285 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in gfx_v9_0_cp_gfx_load_microcode()
3898 const struct gfx_firmware_header_v1_0 *me_hdr = in cik_cp_gfx_load_microcode() local3905 radeon_ucode_print_gfx_hdr(&me_hdr->header); in cik_cp_gfx_load_microcode()3927 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in cik_cp_gfx_load_microcode()3928 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in cik_cp_gfx_load_microcode()3932 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()3933 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3470 const struct gfx_firmware_header_v1_0 *me_hdr = in si_cp_load_microcode() local3477 radeon_ucode_print_gfx_hdr(&me_hdr->header); in si_cp_load_microcode()3499 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()3500 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()