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Searched refs:mdp4_kms (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_kms.c18 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_hw_init() local
77 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_enable_commit() local
83 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_disable_commit() local
94 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_wait_flush() local
121 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_destroy() local
160 int mdp4_disable(struct mdp4_kms *mdp4_kms) in mdp4_disable() argument
172 int mdp4_enable(struct mdp4_kms *mdp4_kms) in mdp4_enable() argument
185 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, in mdp4_modeset_init_intf() argument
278 static int modeset_init(struct mdp4_kms *mdp4_kms) in modeset_init() argument
360 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms, in read_mdp_hw_revision() argument
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H A Dmdp4_irq.c23 struct mdp4_kms *mdp4_kms = container_of(irq, struct mdp4_kms, error_handler); in mdp4_irq_error_handler() local
37 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_preinstall() local
38 mdp4_enable(mdp4_kms); in mdp4_irq_preinstall()
41 mdp4_disable(mdp4_kms); in mdp4_irq_preinstall()
47 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq_postinstall() local
61 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_uninstall() local
62 mdp4_enable(mdp4_kms); in mdp4_irq_uninstall()
70 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq() local
92 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_enable_vblank() local
94 mdp4_enable(mdp4_kms); in mdp4_enable_vblank()
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H A Dmdp4_lcdc_encoder.c50 struct mdp4_kms *mdp4_kms = get_kms(encoder); in setup_phy() local
207 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_lcdc_encoder_mode_set() local
237 mdp4_write(mdp4_kms, REG_MDP4_LCDC_HSYNC_CTRL, in mdp4_lcdc_encoder_mode_set()
242 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_HCTRL, in mdp4_lcdc_encoder_mode_set()
247 mdp4_write(mdp4_kms, REG_MDP4_LCDC_BORDER_CLR, 0); in mdp4_lcdc_encoder_mode_set()
248 mdp4_write(mdp4_kms, REG_MDP4_LCDC_UNDERFLOW_CLR, in mdp4_lcdc_encoder_mode_set()
253 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ACTIVE_HCTL, in mdp4_lcdc_encoder_mode_set()
264 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_lcdc_encoder_disable() local
270 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); in mdp4_lcdc_encoder_disable()
302 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_lcdc_encoder_enable() local
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H A Dmdp4_crtc.c80 struct mdp4_kms *mdp4_kms = get_kms(crtc); in crtc_flush() local
144 static void setup_mixer(struct mdp4_kms *mdp4_kms) in setup_mixer() argument
171 struct mdp4_kms *mdp4_kms = get_kms(crtc); in blend_setup() local
219 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_mode_set_nofb() local
262 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_atomic_disable() local
291 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_atomic_enable() local
358 struct mdp4_kms *mdp4_kms = get_kms(crtc); in update_cursor() local
408 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_cursor_set() local
530 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_wait_for_flush_done() local
559 struct mdp4_kms *mdp4_kms = get_kms(crtc); in mdp4_crtc_set_config() local
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H A Dmdp4_dsi_encoder.c33 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dsi_encoder_mode_set() local
59 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, in mdp4_dsi_encoder_mode_set()
64 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, in mdp4_dsi_encoder_mode_set()
71 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, in mdp4_dsi_encoder_mode_set()
74 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_HCTL, in mdp4_dsi_encoder_mode_set()
78 mdp4_write(mdp4_kms, REG_MDP4_DSI_BORDER_CLR, 0); in mdp4_dsi_encoder_mode_set()
80 mdp4_write(mdp4_kms, REG_MDP4_DSI_ACTIVE_VEND, 0); in mdp4_dsi_encoder_mode_set()
86 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dsi_encoder_disable() local
91 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); in mdp4_dsi_encoder_disable()
109 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dsi_encoder_enable() local
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H A Dmdp4_dtv_encoder.c33 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_mode_set() local
63 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
68 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
73 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
74 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
79 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL, in mdp4_dtv_encoder_mode_set()
83 mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0); in mdp4_dtv_encoder_mode_set()
89 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_disable() local
94 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); in mdp4_dtv_encoder_disable()
116 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_enable() local
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H A Dmdp4_plane.c97 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_cleanup_fb() local
98 struct msm_kms *kms = &mdp4_kms->base.base; in mdp4_plane_cleanup_fb()
143 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_set_scanout() local
144 struct msm_kms *kms = &mdp4_kms->base.base; in mdp4_plane_set_scanout()
165 static void mdp4_write_csc_config(struct mdp4_kms *mdp4_kms, in mdp4_write_csc_config() argument
203 struct mdp4_kms *mdp4_kms = get_kms(plane); in mdp4_plane_mode_set() local
283 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe), in mdp4_plane_mode_set()
287 mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe), in mdp4_plane_mode_set()
291 mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe), in mdp4_plane_mode_set()
295 mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe), in mdp4_plane_mode_set()
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H A Dmdp4_lvds_pll.c19 static struct mdp4_kms *get_kms(struct mdp4_lvds_pll *lvds_pll) in get_kms()
60 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_enable() local
69 mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_PHY_RESET, 0x33); in mpd4_lvds_pll_enable()
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
74 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x01); in mpd4_lvds_pll_enable()
77 while (!mdp4_read(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_LOCKED)) in mpd4_lvds_pll_enable()
86 struct mdp4_kms *mdp4_kms = get_kms(lvds_pll); in mpd4_lvds_pll_disable() local
90 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_CFG0, 0x0); in mpd4_lvds_pll_disable()
91 mdp4_write(mdp4_kms, REG_MDP4_LVDS_PHY_PLL_CTRL_0, 0x0); in mpd4_lvds_pll_disable()
H A Dmdp4_kms.h19 struct mdp4_kms { struct
43 #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) argument
45 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) in mdp4_write() argument
47 writel(data, mdp4_kms->mmio + reg); in mdp4_write()
50 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) in mdp4_read() argument
52 return readl(mdp4_kms->mmio + reg); in mdp4_read()
149 int mdp4_disable(struct mdp4_kms *mdp4_kms);
150 int mdp4_enable(struct mdp4_kms *mdp4_kms);
/linux-6.15/drivers/gpu/drm/msm/
H A DMakefile54 disp/mdp4/mdp4_kms.o \