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Searched refs:mca_msr_reg (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/arch/x86/kernel/cpu/mce/
H A Dcore.c360 if (msr == mca_msr_reg(bank, MCA_STATUS)) in msr_to_offset()
362 if (msr == mca_msr_reg(bank, MCA_ADDR)) in msr_to_offset()
364 if (msr == mca_msr_reg(bank, MCA_MISC)) in msr_to_offset()
687 m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); in mce_read_aux()
832 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); in machine_check_poll()
1277 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); in mce_clear_state()
1881 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl); in __mcheck_cpu_init_clear_banks()
1882 wrmsrl(mca_msr_reg(i, MCA_STATUS), 0); in __mcheck_cpu_init_clear_banks()
1908 rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); in __mcheck_cpu_check_banks()
2439 wrmsrl(mca_msr_reg(i, MCA_CTL), 0); in mce_disable_error_reporting()
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H A Dinject.c750 wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status); in check_hw_inj_possible()
751 rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status); in check_hw_inj_possible()
752 wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), 0); in check_hw_inj_possible()
H A Damd.c556 addr = mca_msr_reg(bank, MCA_MISC); in get_block_address()
853 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), in _log_error_deferred()
854 mca_msr_reg(bank, MCA_ADDR), misc)) in _log_error_deferred()
1235 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC)); in threshold_create_bank()
H A Dinternal.h317 static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg) in mca_msr_reg() function