| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_pch_display.h | 40 struct intel_link_m_n *m_n);
42 struct intel_link_m_n *m_n);
86 struct intel_link_m_n *m_n) in intel_pch_transcoder_get_m1_n1() argument
90 struct intel_link_m_n *m_n) in intel_pch_transcoder_get_m2_n2() argument
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| H A D | intel_display.h | 419 struct intel_link_m_n *m_n);
481 void intel_zero_m_n(struct intel_link_m_n *m_n);
483 const struct intel_link_m_n *m_n,
487 struct intel_link_m_n *m_n,
494 const struct intel_link_m_n *m_n);
497 const struct intel_link_m_n *m_n);
500 struct intel_link_m_n *m_n);
503 struct intel_link_m_n *m_n);
504 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
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| H A D | intel_pch_display.c | 182 const struct intel_link_m_n *m_n) in intel_pch_transcoder_set_m1_n1() argument
187 intel_set_m_n(display, m_n, in intel_pch_transcoder_set_m1_n1()
193 const struct intel_link_m_n *m_n) in intel_pch_transcoder_set_m2_n2() argument
198 intel_set_m_n(display, m_n, in intel_pch_transcoder_set_m2_n2()
204 struct intel_link_m_n *m_n) in intel_pch_transcoder_get_m1_n1() argument
209 intel_get_m_n(display, m_n, in intel_pch_transcoder_get_m1_n1()
215 struct intel_link_m_n *m_n) in intel_pch_transcoder_get_m2_n2() argument
220 intel_get_m_n(display, m_n, in intel_pch_transcoder_get_m2_n2()
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| H A D | intel_crtc_state_dump.c | 36 const struct intel_link_m_n *m_n) in intel_dump_m_n_config() argument
40 m_n->data_m, m_n->data_n, in intel_dump_m_n_config()
41 m_n->link_m, m_n->link_n, m_n->tu); in intel_dump_m_n_config()
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| H A D | intel_display.c | 2541 m_n->tu = 64; in intel_link_compute_m_n()
2542 compute_m_n(&m_n->data_m, &m_n->data_n, in intel_link_compute_m_n()
2546 compute_m_n(&m_n->link_m, &m_n->link_n, in intel_link_compute_m_n()
2579 memset(m_n, 0, sizeof(*m_n)); in intel_zero_m_n()
2580 m_n->tu = 1; in intel_zero_m_n()
2588 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); in intel_set_m_n()
2615 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m1_n1()
2621 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m1_n1()
2635 intel_set_m_n(display, m_n, in intel_cpu_transcoder_set_m2_n2()
3318 intel_get_m_n(display, m_n, in intel_cpu_transcoder_get_m2_n2()
[all …]
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| H A D | intel_drrs.c | 100 &crtc->drrs.m2_n2 : &crtc->drrs.m_n); in intel_drrs_set_refresh_rate_m_n()
168 crtc->drrs.m_n = crtc_state->dp_m_n; in intel_drrs_activate()
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| H A D | intel_dp_mst.c | 173 struct intel_link_m_n *m_n) in intel_dp_mst_compute_m_n() argument
183 m_n); in intel_dp_mst_compute_m_n()
185 m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); in intel_dp_mst_compute_m_n()
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| H A D | intel_display_types.h | 1411 struct intel_link_m_n m_n, m2_n2; member
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| /linux-6.15/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 969 struct cdv_intel_dp_m_n *m_n) in cdv_intel_dp_compute_m_n() argument
971 m_n->tu = 64; in cdv_intel_dp_compute_m_n()
972 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; in cdv_intel_dp_compute_m_n()
973 m_n->gmch_n = link_clock * nlanes; in cdv_intel_dp_compute_m_n()
974 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); in cdv_intel_dp_compute_m_n()
975 m_n->link_m = pixel_clock; in cdv_intel_dp_compute_m_n()
976 m_n->link_n = link_clock; in cdv_intel_dp_compute_m_n()
977 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n); in cdv_intel_dp_compute_m_n()
990 struct cdv_intel_dp_m_n m_n; in cdv_intel_dp_set_m_n() local
1026 m_n.gmch_m); in cdv_intel_dp_set_m_n()
[all …]
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| /linux-6.15/drivers/gpu/drm/hisilicon/kirin/ |
| H A D | dw_drm_dsi.c | 131 u32 m_n = 0; in dsi_calc_phy_rate() local
161 m_n = div_u64(temp, 100000000); in dsi_calc_phy_rate()
164 if (m_n * 6 >= 50) { in dsi_calc_phy_rate()
167 } else if (m_n * 6 >= 30) { in dsi_calc_phy_rate()
175 if (m_n * 6 >= 50) { in dsi_calc_phy_rate()
178 } else if (m_n * 6 >= 30) { in dsi_calc_phy_rate()
181 } else if (m_n * 6 >= 10) { in dsi_calc_phy_rate()
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