Searched refs:lvds_gen_cntl (Results 1 – 6 of 6) sorted by relevance
50 u32 lvds_gen_cntl, tmpPixclksCntl; in radeon_bl_update_status() local67 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS; in radeon_bl_update_status()68 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) { in radeon_bl_update_status()69 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON); in radeon_bl_update_status()73 lvds_gen_cntl |= in radeon_bl_update_status()76 lvds_gen_cntl |= LVDS_ON; in radeon_bl_update_status()77 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN); in radeon_bl_update_status()83 lvds_gen_cntl |= in radeon_bl_update_status()101 lvds_gen_cntl |= LVDS_DISPLAY_DIS; in radeon_bl_update_status()106 lvds_gen_cntl &= ~(LVDS_DIGON); in radeon_bl_update_status()[all …]
1089 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl in radeon_screen_blank()1096 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()1097 rinfo->init_state.lvds_gen_cntl |= in radeon_screen_blank()1134 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()1135 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; in radeon_screen_blank()1333 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_save_state()1894 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; in radeonfb_set_par()1900 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); in radeonfb_set_par()
225 u32 lvds_gen_cntl; member
67 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_lvds_update()107 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | in radeon_legacy_lvds_update()113 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; in radeon_legacy_lvds_update()115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()122 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; in radeon_legacy_lvds_update()124 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; in radeon_legacy_lvds_update()213 lvds_gen_cntl = lvds->lvds_gen_cntl; in radeon_legacy_lvds_mode_set()221 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; in radeon_legacy_lvds_mode_set()222 lvds_gen_cntl &= ~(RADEON_LVDS_ON | in radeon_legacy_lvds_mode_set()235 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; in radeon_legacy_lvds_mode_set()[all …]
1105 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); in radeon_legacy_get_lvds_info_from_regs()1200 lvds->lvds_gen_cntl = 0xff00; in radeon_combios_get_lvds_info()1202 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; in radeon_combios_get_lvds_info()1205 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; in radeon_combios_get_lvds_info()1209 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; in radeon_combios_get_lvds_info()1212 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; in radeon_combios_get_lvds_info()1215 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; in radeon_combios_get_lvds_info()1222 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; in radeon_combios_get_lvds_info()1225 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; in radeon_combios_get_lvds_info()1228 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; in radeon_combios_get_lvds_info()[all …]
384 uint32_t lvds_gen_cntl; member