Home
last modified time | relevance | path

Searched refs:lower_32_bits (Results 1 – 25 of 761) sorted by relevance

12345678910>>...31

/linux-6.15/drivers/firmware/smccc/
H A Dkvm_guest.c36 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
37 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
38 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
39 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
77 ver = lower_32_bits(res.a1); in kvm_arm_target_impl_cpu_init()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c78 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
82 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
136 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
140 lower_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
184 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
209 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
212 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()
286 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
292 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
461 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_v9()
[all …]
H A Dkfd_packet_manager_vi.c70 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
109 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
134 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
137 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
187 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
193 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
265 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
267 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
H A Dkfd_mqd_manager_v12.c128 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
152 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
194 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
197 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
199 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
220 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
336 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
338 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
340 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_vi.c116 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
130 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
132 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
142 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
184 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
187 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
189 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
215 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
370 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
372 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
/linux-6.15/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.c151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
/linux-6.15/drivers/tee/tstee/
H A Dcore.c37 args[0] = lower_32_bits(data->data0); in arg_list_from_ffa_data()
38 args[1] = lower_32_bits(data->data1); in arg_list_from_ffa_data()
39 args[2] = lower_32_bits(data->data2); in arg_list_from_ffa_data()
40 args[3] = lower_32_bits(data->data3); in arg_list_from_ffa_data()
41 args[4] = lower_32_bits(data->data4); in arg_list_from_ffa_data()
190 shm_id = lower_32_bits(param[0].u.value.a); in tstee_invoke_func()
191 req_len = lower_32_bits(param[0].u.value.b); in tstee_invoke_func()
212 ffa_args[TS_RPC_SERVICE_MEM_HANDLE_LSW] = lower_32_bits(handle); in tstee_invoke_func()
281 lower_32_bits(shm->sec_world_id); in tstee_shm_register()
319 lower_32_bits(shm->sec_world_id); in tstee_shm_unregister()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c395 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
964 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
975 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1125 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1134 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1420 lower_32_bits(ring->wptr) | 0x80000000); in vcn_v2_0_dec_ring_set_wptr()
1580 data1 = lower_32_bits(pd_addr); in vcn_v2_0_dec_ring_emit_vm_flush()
1740 lower_32_bits(pd_addr), 0xffffffff); in vcn_v2_0_enc_ring_emit_vm_flush()
1962 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_start_sriov()
2014 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
[all …]
H A Dsdma_v7_0.c148 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
242 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
255 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
261 lower_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
393 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
395 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v7_0_ring_emit_fence()
404 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
542 lower_32_bits(wptr_gpu_addr)); in sdma_v7_0_gfx_resume_instance()
1077 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v7_0_ring_test_ib()
1144 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v7_0_vm_copy_pte()
[all …]
H A Dsdma_v6_0.c148 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
214 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
227 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
232 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
362 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
364 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
373 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
523 lower_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume_instance()
1033 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v6_0_ring_test_ib()
1098 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v6_0_vm_copy_pte()
[all …]
H A Dvce_v4_0.c109 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
110 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
116 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
119 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
122 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
235 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
343 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
344 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
351 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
719 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib()
[all …]
H A Dvcn_v3_0.c534 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
1152 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1163 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
1328 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1338 lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1432 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1449 lower_32_bits(cache_addr)); in vcn_v3_0_start_sriov()
1464 lower_32_bits(cache_addr)); in vcn_v3_0_start_sriov()
1481 lower_32_bits(rb_addr)); in vcn_v3_0_start_sriov()
1495 lower_32_bits(rb_addr)); in vcn_v3_0_start_sriov()
[all …]
H A Dsdma_v5_2.c147 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
220 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
234 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
243 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
247 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
380 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
382 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
391 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
578 lower_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume_instance()
1019 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
[all …]
H A Damdgpu_cper.c297 reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ue_record()
299 reg_data.addr_lo = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ue_record()
301 reg_data.ipid_lo = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ue_record()
303 reg_data.synd_lo = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]); in amdgpu_cper_generate_ue_record()
389 reg_data[CPER_ACA_REG_CTL_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]); in amdgpu_cper_generate_ce_records()
391 reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ce_records()
393 reg_data[CPER_ACA_REG_ADDR_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ce_records()
395 reg_data[CPER_ACA_REG_MISC0_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]); in amdgpu_cper_generate_ce_records()
397 reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); in amdgpu_cper_generate_ce_records()
399 reg_data[CPER_ACA_REG_IPID_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ce_records()
[all …]
H A Dsi_dma.c71 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
214 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
267 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
314 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
315 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
338 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
341 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
421 amdgpu_ring_write(ring, lower_32_bits(addr)); in si_dma_ring_emit_pipeline_sync()
772 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in si_dma_emit_copy_buffer()
773 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in si_dma_emit_copy_buffer()
[all …]
H A Dsdma_v2_4.c313 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
315 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
321 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
554 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
609 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
663 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v2_4_vm_copy_pte()
665 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v2_4_vm_copy_pte()
692 ib->ptr[ib->length_dw++] = lower_32_bits(value); in sdma_v2_4_vm_write_pte()
1191 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in sdma_v2_4_emit_copy_buffer()
1193 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v2_4_emit_copy_buffer()
[all …]
H A Dvcn_v2_5.c628 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
1143 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1154 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
1316 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1325 lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1453 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1503 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1516 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1765 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1856 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
[all …]
H A Dsdma_v5_0.c307 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
410 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
423 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
428 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
561 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
563 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
759 lower_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume_instance()
791 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_gfx_resume_instance()
1163 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v5_0_ring_test_ib()
1228 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v5_0_vm_copy_pte()
[all …]
/linux-6.15/drivers/iio/test/
H A Diio-test-format.c211 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
217 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
223 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
229 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
235 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
241 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
247 values[0] = lower_32_bits(value); in iio_test_iio_format_value_integer_64()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
95 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
99 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
101 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgv100.c47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); in gv100_chan_ramfc_write()
51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in gv100_chan_ramfc_write()
102 nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr)); in gv100_ectx_bind()
122 nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2)); in gv100_ectx_ce_bind()
188 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); in gv100_runl_insert_chan()
190 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); in gv100_runl_insert_chan()
/linux-6.15/drivers/pci/controller/
H A Dpci-xgene.c291 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
295 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
388 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
390 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
392 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
400 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
449 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
452 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
515 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
521 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/linux-6.15/drivers/media/pci/pt3/
H A Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux-6.15/tools/testing/selftests/powerpc/primitives/linux/
H A Dwordpart.h20 #define lower_32_bits(n) ((u32)((n) & 0xffffffff)) macro
48 #define REPEAT_BYTE_U32(x) lower_32_bits(REPEAT_BYTE(x))

12345678910>>...31