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Searched refs:lane_width (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h97 uint8_t lane_width; member
H A Dvega10_hwmgr.c4772 (lane_width == 1) ? "x1" : in vega10_emit_clock_levels()
4773 (lane_width == 2) ? "x2" : in vega10_emit_clock_levels()
4774 (lane_width == 3) ? "x4" : in vega10_emit_clock_levels()
4775 (lane_width == 4) ? "x8" : in vega10_emit_clock_levels()
4776 (lane_width == 5) ? "x12" : in vega10_emit_clock_levels()
4777 (lane_width == 6) ? "x16" : "", in vega10_emit_clock_levels()
4916 (lane_width == 1) ? "x1" : in vega10_print_clock_levels()
4917 (lane_width == 2) ? "x2" : in vega10_print_clock_levels()
4918 (lane_width == 3) ? "x4" : in vega10_print_clock_levels()
4919 (lane_width == 4) ? "x8" : in vega10_print_clock_levels()
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H A Dvega20_hwmgr.c3380 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3474 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3481 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3482 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3483 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3484 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3485 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3486 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3489 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
H A Dprocess_pptables_v1_0.c519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
H A Dvega10_processpptables.c815 pcie_table->entries[i].lane_width = in get_pcie_table()
H A Dsmu7_hwmgr.c677 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c808 uint32_t gen_speed, lane_width; in arcturus_emit_clk_levels() local
896 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in arcturus_emit_clk_levels()
931 (lane_width == 1) ? "x1" : in arcturus_emit_clk_levels()
932 (lane_width == 2) ? "x2" : in arcturus_emit_clk_levels()
933 (lane_width == 3) ? "x4" : in arcturus_emit_clk_levels()
934 (lane_width == 4) ? "x8" : in arcturus_emit_clk_levels()
935 (lane_width == 5) ? "x12" : in arcturus_emit_clk_levels()
936 (lane_width == 6) ? "x16" : "", in arcturus_emit_clk_levels()
H A Dnavi10_ppt.c1268 uint32_t gen_speed, lane_width; in navi10_emit_clk_levels() local
1343 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_emit_clk_levels()
1358 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_emit_clk_levels()
1477 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
1545 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_print_clk_levels()
1560 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_print_clk_levels()
H A Dsienna_cichlid_ppt.c1288 uint32_t gen_speed, lane_width; in sienna_cichlid_print_clk_levels() local
1349 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in sienna_cichlid_print_clk_levels()
1365 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in sienna_cichlid_print_clk_levels()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c1206 uint32_t gen_speed, lane_width; in smu_v13_0_7_print_clk_levels() local
1306 &lane_width); in smu_v13_0_7_print_clk_levels()
1325 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? in smu_v13_0_7_print_clk_levels()
H A Dsmu_v13_0_0_ppt.c1217 uint32_t gen_speed, lane_width; in smu_v13_0_0_print_clk_levels() local
1317 &lane_width); in smu_v13_0_0_print_clk_levels()
1336 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? in smu_v13_0_0_print_clk_levels()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c1081 uint32_t gen_speed, lane_width; in smu_v14_0_2_print_clk_levels() local
1181 &lane_width); in smu_v14_0_2_print_clk_levels()
1202 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? in smu_v14_0_2_print_clk_levels()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dsi_dpm.c4637 u32 lane_width; in si_init_smc_table() local
4708 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4709 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5854 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5862 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/linux-6.15/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5185 u32 lane_width; in si_init_smc_table() local
5256 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5257 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6393 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6401 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6402 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()