| /linux-6.15/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_dp_link_training.c | 1171 int lane_count; in reduce_link_params_in_bw_order() local
1236 int lane_count; in reduce_link_params_in_rate_lane_order() local
1238 lane_count = crtc_state->lane_count; in reduce_link_params_in_rate_lane_order()
1241 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); in reduce_link_params_in_rate_lane_order()
1245 if (lane_count < 0) in reduce_link_params_in_rate_lane_order()
1820 int lane_count; in parse_lane_count() local
1830 lane_count = 0; in parse_lane_count()
1836 switch (lane_count) { in parse_lane_count()
1860 int lane_count; in i915_dp_force_lane_count_write() local
1864 if (lane_count < 0) in i915_dp_force_lane_count_write()
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| H A D | intel_dp.h | 53 int link_rate, int lane_count);
107 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
108 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
140 u32 link_clock, u32 lane_count,
157 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
159 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
206 u8 lane_count);
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| H A D | intel_dpio_phy.c | 599 switch (lane_count) { in bxt_dpio_phy_calc_lane_lat_optim_mask()
607 MISSING_CASE(lane_count); in bxt_dpio_phy_calc_lane_lat_optim_mask()
736 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
749 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
802 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
828 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
845 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
913 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
956 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
965 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
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| H A D | vlv_dsi.c | 59 8 * 100), lane_count); in txbyteclkhs()
66 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1024 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1076 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1129 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1131 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1133 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1225 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
1248 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
1251 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
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| H A D | intel_combo_phy.c | 260 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
267 switch (lane_count) { in intel_combo_phy_power_up_lanes()
278 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
285 switch (lane_count) { in intel_combo_phy_power_up_lanes()
295 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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| H A D | intel_dp_mst.c | 157 overhead = drm_dp_bw_overhead(crtc_state->lane_count, in intel_dp_mst_bw_overhead()
179 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n()
261 crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
364 4 / crtc_state->lane_count); in intel_dp_mtp_tu_compute_config()
408 crtc_state->lane_count = limits->max_lane_count; in mst_stream_compute_link_config()
468 crtc_state->lane_count = limits->max_lane_count; in mst_stream_dsc_compute_link_config()
1145 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1148 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid()
1152 int link_rate, int lane_count) in intel_mst_set_probed_link_params() argument
1155 intel_dp->link.mst_probed_lane_count = lane_count; in intel_mst_set_probed_link_params()
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| H A D | vlv_dsi_pll.c | 48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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| H A D | intel_dp.c | 406 int lane_count; in intel_dp_max_lane_count() local
413 switch (lane_count) { in intel_dp_max_lane_count()
417 return lane_count; in intel_dp_max_lane_count()
419 MISSING_CASE(lane_count); in intel_dp_max_lane_count()
800 u8 lane_count) in intel_dp_link_params_valid() argument
811 if (lane_count == 0 || in intel_dp_link_params_valid()
1787 lane_count); in intel_dp_compute_link_config_wide()
1791 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1978 lane_count <<= 1) { in dsc_compute_link_config()
1988 pipe_config->lane_count = lane_count; in dsc_compute_link_config()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_fixed_vs_pe_retimer.c | 75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
254 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
296 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
326 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
377 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
415 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
455 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
483 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
533 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
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| H A D | link_dp_capability.c | 469 switch (lane_count) { in reduce_lane_count()
518 switch (lane_count) { in increase_lane_count()
588 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
598 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
616 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; in decide_fallback_link_setting_max_bw_policy()
660 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
670 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
679 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
695 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
899 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { in decide_edp_link_settings_with_dsc()
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| H A D | link_dp_training_8b_10b.c | 125 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
186 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
254 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
293 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
306 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
359 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
365 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
366 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
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| H A D | link_dp_training_dpia.c | 299 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
404 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
410 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
465 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
508 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
594 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
688 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
693 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
738 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_transparent() local
771 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_transparent()
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| H A D | link_dp_training.c | 172 lt_settings->link_settings.lane_count, in dp_log_training_result()
467 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
1103 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1160 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1170 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1195 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1421 enum dc_lane_count lane_count = in perform_post_lt_adj_req_sequence() local
1422 lt_settings->link_settings.lane_count; in perform_post_lt_adj_req_sequence()
1635 (cur_link_settings.lane_count <= LANE_COUNT_ONE); in perform_link_training_with_retries()
1690 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; in perform_link_training_with_retries()
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| H A D | link_dp_irq_handler.c | 60 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
66 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
279 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
280 link->verified_link_cap.lane_count; in dp_handle_link_loss()
402 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
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| /linux-6.15/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_core.c | 229 int lane, lane_count, retval; in analogix_dp_link_start() local
231 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
288 lane_count); in analogix_dp_link_start()
317 int lane_count) in analogix_dp_channel_eq_ok() argument
365 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local
368 lane_count = dp->link_train.lane_count; in analogix_dp_get_adjust_training_lane()
388 int lane, lane_count, retval; in analogix_dp_process_clock_recovery() local
394 lane_count = dp->link_train.lane_count; in analogix_dp_process_clock_recovery()
454 int lane_count, retval; in analogix_dp_process_equalizer_training() local
460 lane_count = dp->link_train.lane_count; in analogix_dp_process_equalizer_training()
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| /linux-6.15/drivers/gpu/drm/msm/dp/ |
| H A D | dp_panel.h | 80 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
82 return (lane_count == 1 || in is_lane_count_valid()
83 lane_count == 2 || in is_lane_count_valid()
84 lane_count == 4); in is_lane_count_valid()
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| /linux-6.15/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_dp.c | 262 uint8_t lane_count; member
896 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
909 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
915 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
989 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1006 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1009 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1053 switch (intel_dp->lane_count) { in cdv_intel_dp_mode_set()
1386 intel_dp->lane_count); in cdv_intel_dplink_set_level()
1388 if (ret != intel_dp->lane_count) { in cdv_intel_dplink_set_level()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_validation.c | 255 …return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x100… in dp_link_bandwidth_kbps()
454 enum dc_lane_count lane_count, in get_av_stream_map_lane_count() argument
461 av_stream_map_lane_count = lane_count; in get_av_stream_map_lane_count()
475 enum dc_lane_count lane_count, in get_audio_sdp_overhead() argument
484 audio_sdp_overhead = lane_count * 2 + 8; in get_audio_sdp_overhead()
525 const uint32_t lane_count = 4; in dp_required_hblank_size_bytes() local
531 link_encoding, lane_count, is_mst); in dp_required_hblank_size_bytes()
533 link_encoding, lane_count, is_mst); in dp_required_hblank_size_bytes()
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| /linux-6.15/drivers/gpu/drm/bridge/ |
| H A D | parade-ps8622.c | 53 u32 lane_count; member
183 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
489 &ps8622->lane_count)) { in ps8622_probe()
490 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
491 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
494 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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| /linux-6.15/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dp.c | 74 int lane_count; member
1257 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1264 .lanes = lane_count, in mtk_dp_phy_configure()
1450 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1483 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1521 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1847 lane_count = lane_count / 2; in mtk_dp_training()
1849 if (lane_count == 0) in mtk_dp_training()
1872 if (lane_count == 0) in mtk_dp_training()
1874 lane_count /= 2; in mtk_dp_training()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| H A D | dcn31_dio_link_encoder.c | 475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
659 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
681 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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| /linux-6.15/drivers/gpu/drm/display/ |
| H A D | drm_dp_helper.c | 91 int lane_count) in drm_dp_channel_eq_ok() argument
101 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
111 int lane_count) in drm_dp_clock_recovery_ok() argument
116 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
167 int lane_count) in drm_dp_128b132b_lane_channel_eq_done() argument
176 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_channel_eq_done()
187 int lane_count) in drm_dp_128b132b_lane_symbol_locked() argument
192 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_symbol_locked()
4392 int align = is_mst ? 4 / lane_count : 1; in drm_dp_link_symbol_cycles()
4433 int drm_dp_bw_overhead(int lane_count, int hactive, in drm_dp_bw_overhead() argument
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
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| /linux-6.15/include/drm/display/ |
| H A D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
62 int lane_count);
64 int lane_count);
877 int drm_dp_bw_overhead(int lane_count, int hactive,
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