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Searched refs:lane_base (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c723 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v3_0_config_lpcdrx() local
740 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v3_0_lane_settings() local
754 writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i)); in dsi_phy_hw_v3_0_lane_settings()
755 writel(0x0, lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i)); in dsi_phy_hw_v3_0_lane_settings()
763 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG0(i)); in dsi_phy_hw_v3_0_lane_settings()
764 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG1(i)); in dsi_phy_hw_v3_0_lane_settings()
765 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG2(i)); in dsi_phy_hw_v3_0_lane_settings()
770 lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i)); in dsi_phy_hw_v3_0_lane_settings()
775 lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i)); in dsi_phy_hw_v3_0_lane_settings()
780 writel(0x05, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3)); in dsi_phy_hw_v3_0_lane_settings()
[all …]
H A Ddsi_phy_7nm.c831 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_config_lpcdrx() local
839 writel(0x3, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
841 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0)); in dsi_phy_hw_v4_0_config_lpcdrx()
850 void __iomem *lane_base = phy->lane_base; in dsi_phy_hw_v4_0_lane_settings() local
862 writel(0, lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
863 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i)); in dsi_phy_hw_v4_0_lane_settings()
870 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG0(i)); in dsi_phy_hw_v4_0_lane_settings()
871 writel(0x0, lane_base + REG_DSI_7nm_PHY_LN_CFG1(i)); in dsi_phy_hw_v4_0_lane_settings()
872 writel(i == 4 ? 0x8a : 0xa, lane_base + REG_DSI_7nm_PHY_LN_CFG2(i)); in dsi_phy_hw_v4_0_lane_settings()
873 writel(tx_dctrl[i], lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i)); in dsi_phy_hw_v4_0_lane_settings()
H A Ddsi_phy_14nm.c914 void __iomem *base = phy->lane_base; in dsi_14nm_dphy_set_timing()
955 void __iomem *lane_base = phy->lane_base; in dsi_14nm_phy_enable() local
974 writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i)); in dsi_14nm_phy_enable()
976 writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i)); in dsi_14nm_phy_enable()
978 lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i)); in dsi_14nm_phy_enable()
981 lane_base + REG_DSI_14nm_PHY_LN_CFG3(i)); in dsi_14nm_phy_enable()
982 writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i)); in dsi_14nm_phy_enable()
983 writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i)); in dsi_14nm_phy_enable()
984 writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i)); in dsi_14nm_phy_enable()
H A Ddsi_phy.c670 phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", &phy->lane_size); in dsi_phy_driver_probe()
671 if (IS_ERR(phy->lane_base)) in dsi_phy_driver_probe()
672 return dev_err_probe(dev, PTR_ERR(phy->lane_base), in dsi_phy_driver_probe()
874 if (phy->lane_base) in msm_dsi_phy_snapshot()
876 phy->lane_size, phy->lane_base, in msm_dsi_phy_snapshot()
H A Ddsi_phy.h97 void __iomem *lane_base; member