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Searched refs:lane1 (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,anx7625.yaml72 analogix,lane1-swing:
77 an array of swing register setting for DP tx lane1 PHY.
78 DP TX lane1 swing register setting same with lane0
150 analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dairoha,en7581-pcie-phy.yaml23 - description: PCIE lane1 base address
25 - description: PCIE lane1 detection time base address
H A Dphy-rockchip-usbdp.yaml61 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
63 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
64 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
H A Dqcom,msm8996-qmp-pcie-phy.yaml88 - lane1
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
263 - const: phy-lane1
H A Dpci-armada8k.txt25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
/linux-6.15/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi64 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
H A Dmt8186-corsola-chinchou.dtsi73 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
/linux-6.15/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h243 uint8_t lane1:2; /* Mapping for lane 1 */ member
/linux-6.15/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dtsi188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
H A Darmada-8040-puzzle-m801.dts521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
/linux-6.15/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts411 /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */
423 /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */
H A Drk3568.dtsi192 /* bifurcation; lane1 when using 1+1 */
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi723 reset-names = "lane1";