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Searched refs:lane0 (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
100 /* SERDES4 lane0/1/2/3 select */
/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,anx7625.yaml45 analogix,lane0-swing:
50 an array of swing register setting for DP tx lane0 PHY.
78 DP TX lane1 swing register setting same with lane0
79 swing, please refer lane0-swing property description.
149 analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dairoha,en7581-pcie-phy.yaml22 - description: PCIE lane0 base address
24 - description: PCIE lane0 detection time base address
H A Dphy-rockchip-usbdp.yaml61 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
63 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
H A Dqcom,msm8996-qmp-pcie-phy.yaml87 - lane0
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]
262 - const: phy-lane0
H A Dpci-armada8k.txt25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
/linux-6.15/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi63 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
H A Dmt8186-corsola-chinchou.dtsi72 analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
/linux-6.15/arch/arm64/boot/dts/ti/
H A Dk3-j722s-main.dtsi417 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
418 <0x10 0x3>; /* SERDES1 lane0 select */
H A Dk3-j721e-main.dtsi51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
H A Dk3-j784s4-j742s2-main-common.dtsi82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
H A Dk3-j7200-main.dtsi39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
H A Dk3-am64-main.dtsi58 mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
H A Dk3-j721s2-main.dtsi64 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
/linux-6.15/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h242 uint8_t lane0:2; /* Mapping for lane 0 */ member
/linux-6.15/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dtsi188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
H A Darmada-8040-puzzle-m801.dts521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
/linux-6.15/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts447 /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */
458 /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */
H A Drk3568.dtsi245 /* bifurcation; lane0 when using 1+1 */
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi707 reset-names = "lane0";