Searched refs:jt_offset (Results 1 – 11 of 11) sorted by relevance
186 uint32_t jt_offset; /* jt location */ member205 uint32_t jt_offset; /* jt location */ member
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in radeon_ucode_print_gfx_hdr()149 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in radeon_ucode_print_sdma_hdr()
6434 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6440 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6446 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6452 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6458 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()
208 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()216 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()224 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()232 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()240 table_offset = le32_to_cpu(hdr->jt_offset); in amdgpu_gfx_rlc_setup_cp_table()
182 uint32_t jt_offset; /* jt location */ member227 uint32_t jt_offset; /* jt location */ member306 uint32_t jt_offset; /* jt location */ member
118 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in amdgpu_ucode_print_gfx_hdr()170 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); in amdgpu_ucode_print_rlc_hdr()310 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in amdgpu_ucode_print_sdma_hdr()884 le32_to_cpu(cp_hdr->jt_offset) * 4; in amdgpu_ucode_init_single_fw()1100 (le32_to_cpu(header->jt_offset) * 4); in amdgpu_ucode_patch_jt()
239 info->image_size = le32_to_cpu(header->jt_offset) << 2; in amdgpu_cgs_get_firmware_info()
5796 sdma_hdr->jt_offset, in gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode()5804 sdma_hdr->jt_offset, in gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode()6134 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_pfp_microcode()6211 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_ce_microcode()6288 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v10_0_cp_gfx_load_me_microcode()6665 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); in gfx_v10_0_cp_compute_load_microcode()
1740 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); in gfx_v9_4_3_xcc_cp_compute_load_microcode()1743 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
3090 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); in gfx_v11_0_cp_gfx_load_pfp_microcode()3308 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); in gfx_v11_0_cp_gfx_load_me_microcode()3820 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); in gfx_v11_0_cp_compute_load_microcode()
3483 mec_hdr->jt_offset); in gfx_v9_0_cp_compute_load_microcode()3486 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); in gfx_v9_0_cp_compute_load_microcode()