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Searched refs:ixDIDT_SQ_EDC_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c488 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_S…
489 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_S…
490 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_S…
491 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_S…
492 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_S…
493 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_S…
494 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_S…
495 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_S…
496 …{ ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_S…
841 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); in vega10_didt_set_mask()
[all …]
H A Dsmu7_hwmgr.c116 #define ixDIDT_SQ_EDC_CTRL 0x0013 macro
150 ixDIDT_SQ_EDC_CTRL,
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h7156 #define ixDIDT_SQ_EDC_CTRL … macro
H A Dgc_9_1_offset.h7364 #define ixDIDT_SQ_EDC_CTRL … macro
H A Dgc_9_2_1_offset.h7406 #define ixDIDT_SQ_EDC_CTRL … macro
H A Dgc_9_4_2_offset.h47 #define ixDIDT_SQ_EDC_CTRL … macro
H A Dgc_10_1_0_offset.h11254 #define ixDIDT_SQ_EDC_CTRL … macro
H A Dgc_10_3_0_offset.h13488 #define ixDIDT_SQ_EDC_CTRL … macro