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Searched refs:ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h8094 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_0_1_offset.h12893 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_2_1_0_offset.h13497 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_1_0_offset.h13737 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_6_0_offset.h15104 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_5_0_offset.h766 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_5_1_offset.h745 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_2_1_offset.h14218 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_1_4_offset.h808 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_1_2_offset.h14711 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_2_0_offset.h14264 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_1_5_offset.h14817 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_4_1_0_offset.h16261 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_0_2_offset.h15896 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_1_6_offset.h15308 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_2_0_0_offset.h17161 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
H A Ddcn_3_0_0_offset.h17645 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h17550 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … macro