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Searched refs:ivpu_dbg (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_fw.c450 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", in ivpu_fw_boot_params_print()
452 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", in ivpu_fw_boot_params_print()
454 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", in ivpu_fw_boot_params_print()
456 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", in ivpu_fw_boot_params_print()
478 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", in ivpu_fw_boot_params_print()
500 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", in ivpu_fw_boot_params_print()
505 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", in ivpu_fw_boot_params_print()
507 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", in ivpu_fw_boot_params_print()
511 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", in ivpu_fw_boot_params_print()
527 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", in ivpu_fw_boot_params_print()
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H A Divpu_pm.c216 ivpu_dbg(vdev, PM, "Suspend..\n"); in ivpu_pm_suspend_cb()
232 ivpu_dbg(vdev, PM, "Suspend done.\n"); in ivpu_pm_suspend_cb()
245 ivpu_dbg(vdev, PM, "Resume..\n"); in ivpu_pm_resume_cb()
251 ivpu_dbg(vdev, PM, "Resume done.\n"); in ivpu_pm_resume_cb()
268 ivpu_dbg(vdev, PM, "Runtime suspend..\n"); in ivpu_pm_runtime_suspend_cb()
306 ivpu_dbg(vdev, PM, "Runtime resume..\n"); in ivpu_pm_runtime_resume_cb()
312 ivpu_dbg(vdev, PM, "Runtime resume done.\n"); in ivpu_pm_runtime_resume_cb()
341 ivpu_dbg(vdev, PM, "Pre-reset..\n"); in ivpu_pm_reset_prepare_cb()
350 ivpu_dbg(vdev, PM, "Pre-reset done.\n"); in ivpu_pm_reset_prepare_cb()
357 ivpu_dbg(vdev, PM, "Post-reset..\n"); in ivpu_pm_reset_done_cb()
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H A Divpu_hw_reg_io.h69 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s started (exp_val 0x%x)\n", in ivpu_hw_reg_poll_fld()
80 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) POLL %s %s (reg_val 0x%08x)\n", in ivpu_hw_reg_poll_fld()
92 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_rd32()
102 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_rd64()
110 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val); in ivpu_hw_reg_wr32()
118 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val); in ivpu_hw_reg_wr64()
129 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val); in ivpu_hw_reg_wr32_index()
H A Divpu_mmu.c313 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
317 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
332 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
345 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
364 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", in ivpu_mmu_strtab_alloc()
383 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_cmdq_alloc()
402 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_evtq_alloc()
772 ivpu_dbg(vdev, MMU, "Init..\n"); in ivpu_mmu_init()
796 ivpu_dbg(vdev, MMU, "Init done\n"); in ivpu_mmu_init()
953 ivpu_dbg(vdev, IRQ, "MMU event queue\n"); in ivpu_mmu_irq_evtq_handler()
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H A Divpu_drv.c76 ivpu_dbg(vdev, KREF, "file_priv get: ctx %u refcount %u\n", in ivpu_file_priv_get()
86 ivpu_dbg(vdev, FILE, "file_priv unbind: ctx %u\n", file_priv->ctx.id); in file_priv_unbind()
102 ivpu_dbg(vdev, FILE, "file_priv release: ctx %u bound %d\n", in file_priv_release()
123 ivpu_dbg(vdev, KREF, "file_priv put: ctx %u refcount %u\n", in ivpu_file_priv_put()
272 ivpu_dbg(vdev, FILE, "file_priv create: ctx %u process %s pid %d\n", in ivpu_open()
292 ivpu_dbg(vdev, FILE, "file_priv close: ctx %u process %s pid %d\n", in ivpu_postclose()
346 ivpu_dbg(vdev, PM, "NPU ready message received successfully\n"); in ivpu_wait_for_ready()
505 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
512 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
H A Divpu_job.c135 ivpu_dbg(vdev, JOB, "Command queue %d created, ctx %d\n", cmdq->id, file_priv->ctx.id); in ivpu_cmdq_create()
183 ivpu_dbg(vdev, JOB, "DB %d registered to cmdq %d ctx %d priority %d\n", in ivpu_register_db()
198 ivpu_dbg(vdev, JOB, "Turbo mode enabled"); in ivpu_cmdq_jobq_init()
253 ivpu_dbg(vdev, JOB, "Command queue %d destroyed, ctx %d\n", in ivpu_cmdq_unregister()
259 ivpu_dbg(vdev, JOB, "DB %d unregistered\n", cmdq->db_id); in ivpu_cmdq_unregister()
370 ivpu_dbg(vdev, JOB, "Context ID: %u abort\n", file_priv->ctx.id); in ivpu_context_abort_locked()
393 ivpu_dbg(vdev, JOB, "Job queue full: ctx %d cmdq %d db %d head %d tail %d\n", in ivpu_cmdq_push_job()
473 ivpu_dbg(vdev, JOB, "Job destroyed: id %3u ctx %2d cmdq_id %u engine %d", in ivpu_job_destroy()
567 ivpu_dbg(vdev, JOB, "Job complete: id %3u ctx %2d cmdq_id %u engine %d status 0x%x\n", in ivpu_job_signal_and_destroy()
645 ivpu_dbg(vdev, JOB, "Too many active jobs in ctx %d\n", in ivpu_job_submit()
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H A Divpu_fw_log.c43 ivpu_dbg(vdev, FW_BOOT, "Invalid header size 0x%x\n", log->header_size); in fw_log_from_bo()
47 ivpu_dbg(vdev, FW_BOOT, "Invalid log size 0x%x\n", log->size); in fw_log_from_bo()
54 ivpu_dbg(vdev, FW_BOOT, in fw_log_from_bo()
H A Divpu_hw_btrs.c147 ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config); in read_tile_config_fuse()
331 ivpu_dbg(vdev, PM, "Skipping workpoint request\n"); in ivpu_hw_btrs_wp_drive()
337 ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n", in ivpu_hw_btrs_wp_drive()
536 ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n", in ivpu_hw_btrs_ats_print_lnl()
629 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz", in ivpu_hw_btrs_irq_handler_mtl()
676 ivpu_dbg(vdev, IRQ, "Survivability IRQ\n"); in ivpu_hw_btrs_irq_handler_lnl()
683 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz", in ivpu_hw_btrs_irq_handler_lnl()
H A Divpu_drv.h95 #define ivpu_dbg(vdev, type, fmt, args...) do { \ macro
104 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
H A Divpu_mmu_context.c366 ivpu_dbg(vdev, MMU_MAP, "Split 64K page ctx: %u vpu_addr: 0x%llx\n", ctx->id, vpu_addr); in ivpu_mmu_context_split_64k_page()
390 ivpu_dbg(vdev, MMU_MAP, "Set read-only pages ctx: %u vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_set_pages_ro()
460 ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_map_sgt()
516 ivpu_dbg(vdev, MMU_MAP, "Unmap ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", in ivpu_mmu_context_unmap_sgt()
H A Divpu_ipc.c30 ivpu_dbg(vdev, IPC, in ivpu_ipc_msg_dump()
41 ivpu_dbg(vdev, JSM, in ivpu_jsm_msg_dump()
458 ivpu_dbg(vdev, IPC, "IPC RX msg 0x%x dropped (no consumer)\n", vpu_addr); in ivpu_ipc_irq_handler()
H A Divpu_hw_ip.c833 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in soc_cpu_boot_37xx()
914 ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", in soc_cpu_boot_40xx()
1078 ivpu_dbg(vdev, IRQ, "NOC Firewall interrupt detected, counter %d\n", in irq_noc_firewall_handler()
1099 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_ip_irq_handler_37xx()
1133 ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); in ivpu_hw_ip_irq_handler_40xx()
H A Divpu_hw.c43 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", platform_to_str(platform), platform); in platform_init()
H A Divpu_gem.c29 ivpu_dbg(vdev, BO, in ivpu_dbg_bo()