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Searched refs:intf_cfg (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_encoder_phys_wb.c236 struct dpu_hw_intf_cfg intf_cfg = {0}; in dpu_encoder_phys_wb_setup_ctl() local
242 intf_cfg.intf = DPU_NONE; in dpu_encoder_phys_wb_setup_ctl()
243 intf_cfg.wb = hw_wb->idx; in dpu_encoder_phys_wb_setup_ctl()
244 intf_cfg.cwb = dpu_encoder_helper_get_cwb_mask(phys_enc); in dpu_encoder_phys_wb_setup_ctl()
247 intf_cfg.merge_3d = hw_pp->merge_3d->idx; in dpu_encoder_phys_wb_setup_ctl()
250 intf_cfg.cdm = hw_cdm->idx; in dpu_encoder_phys_wb_setup_ctl()
261 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_wb_setup_ctl()
263 struct dpu_hw_intf_cfg intf_cfg = {0}; in dpu_encoder_phys_wb_setup_ctl() local
265 intf_cfg.intf = DPU_NONE; in dpu_encoder_phys_wb_setup_ctl()
266 intf_cfg.wb = hw_wb->idx; in dpu_encoder_phys_wb_setup_ctl()
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H A Ddpu_encoder_phys_vid.c259 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_phys_vid_setup_timing_engine() local
299 intf_cfg.cdm = phys_enc->hw_cdm->idx; in dpu_encoder_phys_vid_setup_timing_engine()
300 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_phys_vid_setup_timing_engine()
301 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; in dpu_encoder_phys_vid_setup_timing_engine()
302 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_phys_vid_setup_timing_engine()
303 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
304 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
305 if (intf_cfg.mode_3d && phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
306 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
312 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
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H A Ddpu_hw_ctl.c612 u32 intf_cfg = 0; in dpu_hw_ctl_intf_cfg() local
614 intf_cfg |= (cfg->intf & 0xF) << 4; in dpu_hw_ctl_intf_cfg()
617 intf_cfg |= BIT(19); in dpu_hw_ctl_intf_cfg()
618 intf_cfg |= (cfg->mode_3d - 0x1) << 20; in dpu_hw_ctl_intf_cfg()
622 intf_cfg |= (cfg->wb & 0x3) + 2; in dpu_hw_ctl_intf_cfg()
626 intf_cfg &= ~BIT(17); in dpu_hw_ctl_intf_cfg()
627 intf_cfg &= ~(0x3 << 15); in dpu_hw_ctl_intf_cfg()
630 intf_cfg |= BIT(17); in dpu_hw_ctl_intf_cfg()
631 intf_cfg |= ((cfg->stream_sel & 0x3) << 15); in dpu_hw_ctl_intf_cfg()
638 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
H A Ddpu_encoder_phys_cmd.c55 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in _dpu_encoder_phys_cmd_update_intf_cfg() local
62 intf_cfg.intf = phys_enc->hw_intf->idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
63 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; in _dpu_encoder_phys_cmd_update_intf_cfg()
64 intf_cfg.stream_sel = cmd_enc->stream_sel; in _dpu_encoder_phys_cmd_update_intf_cfg()
65 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
66 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
67 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
75 if (intf_cfg.dsc != 0) in _dpu_encoder_phys_cmd_update_intf_cfg()
H A Ddpu_hw_intf.c114 u32 intf_cfg, intf_cfg2 = 0; in dpu_hw_intf_setup_timing_engine() local
120 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
156 intf_cfg |= INTF_CFG_ACTIVE_H_EN; in dpu_hw_intf_setup_timing_engine()
162 intf_cfg |= INTF_CFG_ACTIVE_V_EN; in dpu_hw_intf_setup_timing_engine()
204 intf_cfg |= INTF_CFG_ACTIVE_H_EN | INTF_CFG_ACTIVE_V_EN; in dpu_hw_intf_setup_timing_engine()
239 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
H A Ddpu_encoder.c2238 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_helper_phys_cleanup() local
2304 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_helper_phys_cleanup()
2305 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_helper_phys_cleanup()
2306 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); in dpu_encoder_helper_phys_cleanup()
2307 intf_cfg.cwb = dpu_enc->cwb_mask; in dpu_encoder_helper_phys_cleanup()
2310 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_helper_phys_cleanup()
2312 intf_cfg.wb = phys_enc->hw_wb->idx; in dpu_encoder_helper_phys_cleanup()
2315 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_helper_phys_cleanup()
2318 ctl->ops.reset_intf_cfg(ctl, &intf_cfg); in dpu_encoder_helper_phys_cleanup()
/linux-6.15/sound/soc/qcom/qdsp6/
H A Daudioreach.c655 intf_cfg = p; in audioreach_display_port_set_media_format()
656 param_data = &intf_cfg->param_data; in audioreach_display_port_set_media_format()
663 intf_cfg->cfg.mst_idx = 0; in audioreach_display_port_set_media_format()
664 intf_cfg->cfg.dptx_idx = cfg->dp_idx; in audioreach_display_port_set_media_format()
678 struct apm_codec_dma_module_intf_cfg *intf_cfg; in audioreach_codec_dma_set_media_format() local
724 intf_cfg = p; in audioreach_codec_dma_set_media_format()
725 param_data = &intf_cfg->param_data; in audioreach_codec_dma_set_media_format()
948 struct apm_i2s_module_intf_cfg *intf_cfg; in audioreach_i2s_set_media_format() local
966 intf_cfg = p; in audioreach_i2s_set_media_format()
968 param_data = &intf_cfg->param_data; in audioreach_i2s_set_media_format()
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