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Searched refs:intel_de_write (Results 1 – 25 of 58) sorted by relevance

123

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c576 intel_de_write(display, in intel_dsc_pps_configure()
579 intel_de_write(display, in intel_dsc_pps_configure()
582 intel_de_write(display, in intel_dsc_pps_configure()
585 intel_de_write(display, in intel_dsc_pps_configure()
621 intel_de_write(display, in intel_dsc_pps_configure()
626 intel_de_write(display, in intel_dsc_pps_configure()
631 intel_de_write(display, in intel_dsc_pps_configure()
643 intel_de_write(display, in intel_dsc_pps_configure()
648 intel_de_write(display, in intel_dsc_pps_configure()
653 intel_de_write(display, in intel_dsc_pps_configure()
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H A Dintel_fdi.c482 intel_de_write(display, reg, temp); in intel_fdi_normal_train()
529 intel_de_write(display, reg, temp); in ilk_fdi_link_train()
585 intel_de_write(display, reg, in ilk_fdi_link_train()
628 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
673 intel_de_write(display, reg, in gen6_fdi_link_train()
697 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
708 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
724 intel_de_write(display, reg, in gen6_fdi_link_train()
765 intel_de_write(display, reg, temp); in ivb_manual_fdi_link_train()
819 intel_de_write(display, reg, in ivb_manual_fdi_link_train()
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H A Di9xx_display_sr.c47 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
48 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
51 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
54 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
57 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
58 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
61 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
96 intel_de_write(display, DSPARB(display), display->restore.saveDSPARB); in i9xx_display_sr_restore()
H A Dvlv_dsi.c112 intel_de_write(display, reg, val); in write_data()
173 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
183 intel_de_write(display, ctrl_reg, in intel_dsi_host_transfer()
659 intel_de_write(display, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
803 intel_de_write(display, in intel_dsi_pre_enable()
913 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
1263 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1267 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1337 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1343 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
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H A Dintel_tv.c1418 intel_de_write(display, TV_CSC_Y, in set_color_conversion()
1420 intel_de_write(display, TV_CSC_Y2, in set_color_conversion()
1422 intel_de_write(display, TV_CSC_U, in set_color_conversion()
1424 intel_de_write(display, TV_CSC_U2, in set_color_conversion()
1426 intel_de_write(display, TV_CSC_V, in set_color_conversion()
1428 intel_de_write(display, TV_CSC_V2, in set_color_conversion()
1541 intel_de_write(display, TV_CLR_LEVEL, in intel_tv_pre_enable()
1566 intel_de_write(display, TV_H_LUMA(i), in intel_tv_pre_enable()
1569 intel_de_write(display, TV_H_CHROMA(i), in intel_tv_pre_enable()
1572 intel_de_write(display, TV_V_LUMA(i), in intel_tv_pre_enable()
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H A Dintel_vrr.c367 intel_de_write(display, in intel_vrr_set_transcoder_timings()
373 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
383 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
385 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
387 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
393 intel_de_write(display, in intel_vrr_set_transcoder_timings()
472 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
476 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
480 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
493 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_disable()
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H A Dintel_pch_display.c136 intel_de_write(dev_priv, hdmi_reg, val); in ibx_sanitize_pch_hdmi_port()
155 intel_de_write(dev_priv, dp_reg, val); in ibx_sanitize_pch_dp_port()
232 intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
236 intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
243 intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
276 intel_de_write(display, reg, val); in ilk_enable_pch_transcoder()
311 intel_de_write(display, reg, val | TRANS_ENABLE); in ilk_enable_pch_transcoder()
396 intel_de_write(display, PCH_DPLL_SEL, temp); in ilk_pch_enable()
447 intel_de_write(display, reg, temp); in ilk_pch_enable()
568 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
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H A Dintel_display_irq.c262 intel_de_write(display, SDEIMR, sdeimr); in ibx_display_interrupt_update()
519 intel_de_write(display, in i9xx_pipestat_irq_reset()
942 intel_de_write(display, SDEIIR, pch_iir); in ilk_display_irq_handler()
1574 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_enable()
1584 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_disable()
1874 intel_de_write(display, VLV_EIR, *eir); in vlv_display_error_irq_ack()
1883 intel_de_write(display, VLV_EMR, emr); in vlv_display_error_irq_ack()
1951 intel_de_write(display, DPINVGTT, in vlv_display_irq_postinstall()
1955 intel_de_write(display, DPINVGTT, in vlv_display_irq_postinstall()
2028 intel_de_write(display, in gen11_display_irq_reset()
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H A Dintel_backlight.c254 intel_de_write(display, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
498 intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2); in lpt_enable_backlight()
579 intel_de_write(display, BLC_PWM_CTL, 0); in i9xx_enable_backlight()
592 intel_de_write(display, BLC_PWM_CTL, ctl); in i9xx_enable_backlight()
622 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
630 intel_de_write(display, BLC_PWM_CTL, ctl); in i965_enable_backlight()
637 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
693 intel_de_write(display, UTIL_PIN_CTL, val); in bxt_enable_backlight()
699 intel_de_write(display, UTIL_PIN_CTL, in bxt_enable_backlight()
1275 intel_de_write(display, BLC_PWM_PCH_CTL1, in lpt_setup_backlight()
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H A Dg4x_hdmi.c62 intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); in intel_hdmi_prepare()
233 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in g4x_hdmi_enable_port()
296 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
298 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
310 intel_de_write(display, intel_hdmi->hdmi_reg, in ibx_enable_hdmi()
318 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
320 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
358 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
365 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
396 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in intel_disable_hdmi()
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H A Dicl_dsi.c326 intel_de_write(display, dss_ctl1_reg, dss_ctl1); in configure_dual_link_mode()
379 intel_de_write(display, ADL_MIPIO_DW(port, 8), in gen11_dsi_program_esc_clk_div()
617 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_gate_clocks()
633 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_ungate_clocks()
671 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); in gen11_dsi_map_pll()
833 intel_de_write(display, in gen11_dsi_configure_transcoder()
950 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
979 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
994 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
1009 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
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H A Dintel_crt.c222 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_set_dpms()
504 intel_de_write(display, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
514 intel_de_write(display, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
561 intel_de_write(display, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
567 intel_de_write(display, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
627 intel_de_write(display, PORT_HOTPLUG_STAT(display), in intel_crt_detect_hotplug()
769 intel_de_write(display, in intel_crt_load_detect()
803 intel_de_write(display, in intel_crt_load_detect()
983 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_reset()
1042 intel_de_write(display, adpa_reg, in intel_crt_init()
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H A Dintel_fifo_underrun.c107 intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
126 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
161 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
174 intel_de_write(display, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
230 intel_de_write(display, SERR_INT, in cpt_check_pch_fifo_underruns()
246 intel_de_write(display, SERR_INT, in cpt_set_fifo_underrun_reporting()
H A Dintel_dp_test.c235 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
243 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
249 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
255 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
267 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val); in intel_dp_phy_pattern_update()
269 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val); in intel_dp_phy_pattern_update()
271 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val); in intel_dp_phy_pattern_update()
272 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
285 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
297 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
H A Dintel_fbc.c322 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
340 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
343 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
345 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
349 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
387 intel_de_write(display, FBC_CFB_BASE, in i8xx_fbc_program_cfb()
389 intel_de_write(display, FBC_LL_BASE, in i8xx_fbc_program_cfb()
463 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
466 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
497 intel_de_write(display, DPFC_CB_BASE, in g4x_fbc_program_cfb()
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H A Dintel_hdmi.c297 intel_de_write(display, reg, val); in ibx_write_infoframe()
312 intel_de_write(display, reg, val); in ibx_write_infoframe()
375 intel_de_write(display, reg, val); in cpt_write_infoframe()
390 intel_de_write(display, reg, val); in cpt_write_infoframe()
446 intel_de_write(display, reg, val); in vlv_write_infoframe()
449 intel_de_write(display, in vlv_write_infoframe()
455 intel_de_write(display, in vlv_write_infoframe()
462 intel_de_write(display, reg, val); in vlv_write_infoframe()
523 intel_de_write(display, in hsw_write_infoframe()
530 intel_de_write(display, in hsw_write_infoframe()
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H A Dintel_combo_phy.c88 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
89 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
345 intel_de_write(display, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
353 intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
358 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
H A Dg4x_dp.c215 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
230 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
248 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_off()
439 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
443 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
463 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
493 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_enable()
512 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_disable()
620 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in cpt_set_link_train()
648 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_set_link_train()
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H A Dintel_hdcp.c563 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
572 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
580 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
589 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
600 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
608 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
617 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
626 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
705 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
848 intel_de_write(display, in intel_hdcp_auth()
[all …]
H A Dvlv_dsi_pll.c374 intel_de_write(display, MIPI_CTRL(display, port), in vlv_dsi_reset_clocks()
418 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
420 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
475 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
546 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
584 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
590 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); in bxt_dsi_reset_clocks()
H A Dintel_dkl_phy.c29 intel_de_write(display, in dkl_phy_set_hip_idx()
72 intel_de_write(display, DKL_REG_MMIO(reg), val); in intel_dkl_phy_write()
H A Dintel_pps.c775 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
846 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
988 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1004 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1016 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1063 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
1109 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_on()
1130 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_off()
1191 intel_de_write(display, pp_on_reg, 0); in vlv_detach_power_sequencer()
1630 intel_de_write(display, regs.pp_ctrl, pp); in pps_init_registers()
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H A Dintel_pch_refclk.c110 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); in lpt_disable_iclkip()
227 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); in lpt_program_iclkip()
617 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
636 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
647 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
661 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
H A Dintel_pipe_crc.c189 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_pipe_crc_ctl_reg()
252 intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); in vlv_undo_pipe_scramble_reset()
618 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); in intel_crtc_set_crc_source()
653 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); in intel_crtc_enable_pipe_crc()
668 intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0); in intel_crtc_disable_pipe_crc()
H A Dintel_display_power_well.c662 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
673 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
1192 intel_de_write(display, MI_ARB_VLV, in vlv_init_display_clock_gating()
1194 intel_de_write(display, CBR1_VLV, 0); in vlv_init_display_clock_gating()
1197 intel_de_write(display, RAWCLK_FREQ_VLV, in vlv_init_display_clock_gating()
1484 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_enable()
1514 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_disable()
1612 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_ch()
1645 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_lanes()
1729 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_pipe_power_well_sync_hw()
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