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Searched refs:intel_de_rmw (Results 1 – 25 of 46) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_wa.c14 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); in gen11_display_wa_apply()
20 intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); in xe_d_display_wa_apply()
26 intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); in adlp_display_wa_apply()
29 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); in adlp_display_wa_apply()
H A Dintel_cmtg.c136 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A), in intel_cmtg_disable()
140 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B), in intel_cmtg_disable()
145 intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0); in intel_cmtg_disable()
152 intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0); in intel_cmtg_disable()
158 intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set); in intel_cmtg_disable()
H A Dintel_fdi.c572 intel_de_rmw(display, FDI_TX_CTL(pipe), in ilk_fdi_link_train()
574 intel_de_rmw(display, FDI_RX_CTL(pipe), in ilk_fdi_link_train()
663 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
714 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
835 intel_de_rmw(display, FDI_TX_CTL(pipe), in ivb_manual_fdi_link_train()
838 intel_de_rmw(display, FDI_RX_CTL(pipe), in ivb_manual_fdi_link_train()
951 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
988 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
1016 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_disable()
1043 intel_de_rmw(display, reg, 0, FDI_PCDCLK); in ilk_fdi_pll_enable()
[all …]
H A Dicl_dsi.c231 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, in icl_dsi_frame_update()
408 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), in gen11_dsi_enable_io_power()
489 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, in gen11_dsi_voltage_swing_program_seq()
565 intel_de_rmw(display, ICL_DPHY_CHKN(phy), in gen11_dsi_setup_dphy_timings()
793 intel_de_rmw(display, in gen11_dsi_configure_transcoder()
1063 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), in gen11_dsi_setup_timeouts()
1077 intel_de_rmw(display, DSI_TA_TO(dsi_trans), in gen11_dsi_setup_timeouts()
1230 intel_de_rmw(display, CHICKEN_PAR1_1, in icl_apply_kvmr_pipe_a_wa()
1324 intel_de_rmw(display, DSI_CMD_FRMCTL(port), in gen11_dsi_deconfigure_trancoder()
1345 intel_de_rmw(display, in gen11_dsi_deconfigure_trancoder()
[all …]
H A Dintel_combo_phy.c85 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
303 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
364 intel_de_rmw(display, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
367 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
368 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
399 intel_de_rmw(display, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
403 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()
H A Dintel_audio.c294 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_disable()
312 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
326 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
420 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_disable()
628 intel_de_rmw(display, regs.aud_config, in ibx_audio_codec_disable()
637 intel_de_rmw(display, regs.aud_cntrl_st2, in ibx_audio_codec_disable()
666 intel_de_rmw(display, regs.aud_cntrl_st2, in ibx_audio_codec_enable()
675 intel_de_rmw(display, regs.aud_config, in ibx_audio_codec_enable()
1063 intel_de_rmw(display, AUD_PIN_BUF_CTL, in intel_audio_component_get_power()
1099 intel_de_rmw(display, HSW_AUD_CHICKENBIT, in intel_audio_component_codec_wake_override()
[all …]
H A Dintel_dpt_common.c25 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
31 intel_de_rmw(i915, CHICKEN_MISC_2, in intel_dpt_configure()
H A Dvlv_dsi.c347 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
386 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
391 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
516 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
603 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); in vlv_dsi_clear_device_ready()
625 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
629 intel_de_rmw(display, VLV_CHICKEN_3, in intel_dsi_port_enable()
675 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); in intel_dsi_port_disable()
767 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), in intel_dsi_pre_enable()
925 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), in intel_dsi_post_disable()
[all …]
H A Dintel_dpio_phy.c321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
331 intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
345 intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
436 intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy), in _bxt_dpio_phy_init()
439 intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy), in _bxt_dpio_phy_init()
443 intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0, in _bxt_dpio_phy_init()
447 intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0, in _bxt_dpio_phy_init()
467 intel_de_rmw(display, BXT_PORT_REF_DW8(phy), in _bxt_dpio_phy_init()
474 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); in _bxt_dpio_phy_init()
483 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); in bxt_dpio_phy_uninit()
[all …]
H A Dintel_display_power_well.c359 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); in hsw_power_well_enable()
518 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), in icl_tc_phy_aux_power_well_enable()
521 intel_de_rmw(display, regs->driver, in icl_tc_phy_aux_power_well_enable()
792 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); in tgl_disable_dc3co()
832 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in gen9_enable_dc5()
863 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in skl_enable_dc6()
1186 intel_de_rmw(display, DSPCLK_GATE_D(display), in vlv_init_display_clock_gating()
1306 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); in vlv_dpio_cmn_power_well_enable()
1318 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); in vlv_dpio_cmn_power_well_disable()
1837 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_enable()
[all …]
H A Dintel_ddi.c1270 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phy_set_signal_levels()
1553 intel_de_rmw(i915, reg, clk_off, 0); in _icl_ddi_enable_clock()
1563 intel_de_rmw(i915, reg, 0, clk_off); in _icl_ddi_disable_clock()
1842 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_enable_clock()
1856 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_disable_clock()
1946 intel_de_rmw(i915, DPLL_CTRL2, in skl_ddi_enable_clock()
1962 intel_de_rmw(i915, DPLL_CTRL2, in skl_ddi_disable_clock()
2544 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), in intel_ddi_mso_configure()
2570 intel_de_rmw(dev_priv, reg, 0, set_bits); in mtl_ddi_enable_d2d()
3071 intel_de_rmw(dev_priv, reg, clr_bits, 0); in mtl_ddi_disable_d2d()
[all …]
H A Dintel_display_power.c1048 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1121 intel_de_rmw(display, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1152 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1381 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1625 intel_de_rmw(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1644 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1666 intel_de_rmw(display, DC_STATE_EN, in icl_display_core_init()
1698 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, in icl_display_core_init()
1708 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1710 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
[all …]
H A Dintel_pch_display.c332 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); in ilk_disable_pch_transcoder()
340 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), in ilk_disable_pch_transcoder()
469 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), in ilk_pch_post_disable()
474 intel_de_rmw(dev_priv, PCH_DPLL_SEL, in ilk_pch_post_disable()
587 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); in lpt_disable_pch_transcoder()
594 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
H A Dintel_dmc.c411 intel_de_rmw(display, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
461 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
465 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
476 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
496 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
498 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
509 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
511 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
H A Dintel_psr.c466 val = intel_de_rmw(dev_priv, in intel_psr_irq_handler()
1005 intel_de_rmw(display, in dg2_activate_panel_replay()
1819 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1822 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1896 intel_de_rmw(display, in intel_psr_enable_source()
1935 intel_de_rmw(display, in intel_psr_enable_source()
2067 val = intel_de_rmw(display, in intel_psr_exit()
2073 val = intel_de_rmw(display, in intel_psr_exit()
2136 intel_de_rmw(display, in intel_psr_disable_locked()
2140 intel_de_rmw(display, CLKGATE_DIS_MISC, in intel_psr_disable_locked()
[all …]
H A Dintel_dpll_mgr.c1372 intel_de_rmw(display, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
2056 intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
2074 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
2078 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1), in bxt_ddi_pll_enable()
2082 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2), in bxt_ddi_pll_enable()
2086 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3), in bxt_ddi_pll_enable()
2098 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8), in bxt_ddi_pll_enable()
2101 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9), in bxt_ddi_pll_enable()
3796 intel_de_rmw(display, div0_reg, in icl_dpll_write()
3813 intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port), in icl_mg_pll_write()
[all …]
H A Dvlv_dsi_pll.c308 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0); in bxt_dsi_pll_disable()
558 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE); in bxt_dsi_pll_enable()
586 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); in bxt_dsi_reset_clocks()
588 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); in bxt_dsi_reset_clocks()
H A Dintel_cx0_phy.c88 intel_de_rmw(display, in intel_cx0_program_msgbus_timer()
130 intel_de_rmw(display, in intel_clear_response_ready_flag()
2754 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in intel_program_port_clock_ctl()
2775 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_program_port_clock_ctl()
2812 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2827 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2845 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), in intel_cx0_setup_powerdown()
2848 intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port), in intel_cx0_setup_powerdown()
2911 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), in intel_cx0_phy_lane_reset()
3064 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in __intel_cx0pll_enable()
[all …]
H A Dintel_pmdemand.c131 intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
503 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0), in intel_pmdemand_program_dbuf()
506 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_dbuf()
615 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_params()
H A Dintel_hotplug_irq.c1006 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_detection_setup()
1015 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_enable_detection()
1022 intel_de_rmw(i915, SHOTPLUG_CTL_TC, in mtp_tc_hpd_detection_setup()
1031 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_tc_hpd_enable_detection()
1047 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val); in mtp_hpd_invert()
1106 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), in _xelpdp_pica_hpd_detection_setup()
1145 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs, in xelpdp_hpd_irq_setup()
1382 intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd); in g45_hpd_peg_band_gap_wa()
H A Dintel_dsi_vbt.c347 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI, in icl_native_gpio_set_value()
357 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), PANEL_POWER_ON, in icl_native_gpio_set_value()
364 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
371 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
380 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
H A Dintel_dkl_phy.c93 intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set); in intel_dkl_phy_rmw()
H A Dg4x_hdmi.c250 intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); in g4x_hdmi_audio_enable()
268 intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); in g4x_hdmi_audio_disable()
351 intel_de_rmw(display, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
368 intel_de_rmw(display, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
H A Dintel_dvo.c195 intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0); in intel_disable_dvo()
212 intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE); in intel_enable_dvo()
462 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0, in intel_dvo_init_dev()
H A Dintel_lvds.c329 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); in intel_enable_lvds()
331 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); in intel_enable_lvds()
349 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); in intel_disable_lvds()
354 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); in intel_disable_lvds()

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