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Searched refs:intel_de_read (Results 1 – 25 of 65) sorted by relevance

123

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c40 cur_state = intel_de_read(display, in assert_fdi_tx()
474 temp = intel_de_read(display, reg); in intel_fdi_normal_train()
485 temp = intel_de_read(display, reg); in intel_fdi_normal_train()
526 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
530 intel_de_read(display, reg); in ilk_fdi_link_train()
535 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
543 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
625 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
635 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
649 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
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H A Dintel_pch_display.c113 val = intel_de_read(display, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
123 u32 val = intel_de_read(dev_priv, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
142 u32 val = intel_de_read(dev_priv, dp_reg); in ibx_sanitize_pch_dp_port()
267 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
280 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
388 temp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_enable()
430 temp = intel_de_read(display, reg); in ilk_pch_enable()
514 tmp = intel_de_read(display, FDI_RX_CTL(pipe)); in ilk_pch_get_config()
528 tmp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_get_config()
571 pipeconf_val = intel_de_read(dev_priv, in lpt_enable_pch_transcoder()
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H A Di9xx_display_sr.c22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
36 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
74 display->restore.saveDSPARB = intel_de_read(display, DSPARB(display)); in i9xx_display_sr_save()
H A Dintel_combo_phy.c60 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
96 u32 val = intel_de_read(display, reg); in check_phy_reg()
154 return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
156 return !(intel_de_read(display, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
158 (intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
335 val = intel_de_read(display, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
349 val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
355 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
H A Dintel_backlight.c253 tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
353 tmp = intel_de_read(display, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
574 ctl = intel_de_read(display, BLC_PWM_CTL); in i9xx_enable_backlight()
616 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
687 val = intel_de_read(display, UTIL_PIN_CTL); in bxt_enable_backlight()
1326 ctl = intel_de_read(display, BLC_PWM_CTL); in i9xx_setup_backlight()
1368 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_setup_backlight()
1372 ctl = intel_de_read(display, BLC_PWM_CTL); in i965_setup_backlight()
1436 pwm_ctl = intel_de_read(display, in bxt_setup_backlight()
1441 val = intel_de_read(display, UTIL_PIN_CTL); in bxt_setup_backlight()
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H A Dintel_crt.c97 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
134 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
520 adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
571 adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
719 save_bclrpat = intel_de_read(display, in intel_crt_load_detect()
721 save_vtotal = intel_de_read(display, in intel_crt_load_detect()
723 vblank = intel_de_read(display, in intel_crt_load_detect()
736 u32 transconf = intel_de_read(display, in intel_crt_load_detect()
764 u32 vsync = intel_de_read(display, in intel_crt_load_detect()
980 adpa = intel_de_read(display, crt->adpa_reg); in intel_crt_reset()
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H A Dintel_display_power_well.c593 val = intel_de_read(display, regs->driver); in hsw_power_well_enabled()
603 val |= intel_de_read(display, regs->bios); in hsw_power_well_enabled()
616 intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc9()
620 intel_de_read(display, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
642 intel_de_read(display, DC_STATE_EN) & in assert_can_disable_dc9()
670 v = intel_de_read(display, DC_STATE_EN); in gen9_write_dc_state()
765 val = intel_de_read(display, DC_STATE_EN); in gen9_set_dc_state()
816 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc5()
843 (intel_de_read(display, UTIL_PIN_CTL) & in assert_can_enable_dc6()
848 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc6()
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H A Dintel_pps.c300 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
626 intel_de_read(display, pp_stat_reg), in wait_panel_status()
627 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
634 intel_de_read(display, pp_stat_reg), in wait_panel_status()
635 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
781 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
782 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
854 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
1680 intel_de_read(display, regs.pp_on), in pps_init_registers()
1681 intel_de_read(display, regs.pp_off), in pps_init_registers()
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H A Dintel_display_irq.c183 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
250 u32 sdeimr = intel_de_read(display, SDEIMR); in ibx_display_interrupt_update()
706 intel_de_read(display, FDI_RX_IIR(pipe))); in ibx_irq_handler()
796 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_serr_int_handler()
840 intel_de_read(display, FDI_RX_IIR(pipe))); in cpt_irq_handler()
934 u32 pch_iir = intel_de_read(display, SDEIIR); in ilk_display_irq_handler()
990 u32 pch_iir = intel_de_read(display, SDEIIR); in ivb_display_irq_handler()
1339 *pch_iir = intel_de_read(display, SDEIIR); in gen8_read_and_ack_pch_irqs()
1830 tmp = intel_de_read(display, DPINVGTT); in vlv_page_table_error_irq_ack()
1869 *eir = intel_de_read(display, VLV_EIR); in vlv_display_error_irq_ack()
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H A Dintel_dpll_mgr.c539 val = intel_de_read(display, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
763 val = intel_de_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
784 val = intel_de_read(display, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1445 val = intel_de_read(display, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1449 val = intel_de_read(display, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1484 val = intel_de_read(display, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1488 val = intel_de_read(display, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
2225 hw_state->pcsdw12 = intel_de_read(display, in bxt_ddi_pll_get_hw_state()
2231 intel_de_read(display, in bxt_ddi_pll_get_hw_state()
3561 val = intel_de_read(display, enable_reg); in mg_pll_get_hw_state()
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H A Dicl_dsi.c187 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
299 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); in configure_dual_link_mode()
457 tmp = intel_de_read(display, in gen11_dsi_config_phy_lanes_sequence()
613 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_gate_clocks()
629 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_ungate_clocks()
645 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_is_clock_enabled()
666 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
806 tmp = intel_de_read(display, in gen11_dsi_configure_transcoder()
1098 tmp = intel_de_read(display, UTIL_PIN_CTL); in gen11_dsi_config_util_pin()
1331 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
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H A Dintel_pch_refclk.c18 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
24 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
235 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
398 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in spll_uses_pch_ssc()
399 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
418 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in wrpll_uses_pch_ssc()
419 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
536 temp = intel_de_read(display, PCH_DPLL(pll->info->id)); in ilk_init_pch_refclk()
557 val = intel_de_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
H A Di9xx_plane.c567 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in g4x_primary_capture_error()
579 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i965_plane_capture_error()
590 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i8xx_plane_capture_error()
739 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_plane_get_hw_state()
1159 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1180 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1185 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1188 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1193 base = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1199 val = intel_de_read(display, PIPESRC(display, pipe)); in i9xx_get_initial_plane_config()
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H A Dintel_cmtg.c98 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); in intel_cmtg_transcoder_is_secondary()
108 val = intel_de_read(display, TRANS_CMTG_CTL_A); in intel_cmtg_get_config()
112 val = intel_de_read(display, TRANS_CMTG_CTL_B); in intel_cmtg_get_config()
H A Dintel_fifo_underrun.c103 if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
130 if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
154 u32 err_int = intel_de_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
185 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
223 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
256 if (old && intel_de_read(display, SERR_INT) & in cpt_set_fifo_underrun_reporting()
H A Dvlv_dsi.c123 u32 val = intel_de_read(display, reg); in read_data()
639 temp = intel_de_read(display, port_ctrl); in intel_dsi_port_enable()
976 enabled = intel_de_read(display, in intel_dsi_get_hw_state()
981 u32 tmp = intel_de_read(display, in intel_dsi_get_hw_state()
1056 intel_de_read(display, in bxt_dsi_get_pipe_config()
1059 intel_de_read(display, in bxt_dsi_get_pipe_config()
1062 intel_de_read(display, in bxt_dsi_get_pipe_config()
1066 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1073 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1335 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
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H A Dintel_tc.c306 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
503 pch_isr = intel_de_read(i915, SDEISR); in icl_tc_phy_hpd_live_status()
741 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
789 cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
790 pch_isr = intel_de_read(i915, SDEISR); in adlp_tc_phy_hpd_live_status()
819 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
852 val = intel_de_read(i915, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
979 pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR); in xelpdp_tc_phy_hpd_live_status()
980 pch_isr = intel_de_read(i915, SDEISR); in xelpdp_tc_phy_hpd_live_status()
1062 val = intel_de_read(display, reg); in __xelpdp_tc_phy_enable_tcss_power()
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H A Dintel_lvds.c92 val = intel_de_read(i915, lvds_reg); in intel_lvds_port_enabled()
132 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
150 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); in intel_lvds_get_config()
163 pps->powerdown_on_reset = intel_de_read(dev_priv, in intel_lvds_pps_get_hw_state()
166 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
171 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
175 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
217 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); in intel_lvds_pps_init_hw()
822 val = intel_de_read(i915, lvds_encoder->reg); in compute_is_dual_link_lvds()
874 lvds = intel_de_read(i915, lvds_reg); in intel_lvds_init()
H A Dintel_display_power.c1157 u32 val = intel_de_read(display, LCPLL_CTL); in hsw_assert_cdclk()
1229 return intel_de_read(display, D_COMP_HSW); in hsw_read_dcomp()
1231 return intel_de_read(display, D_COMP_BDW); in hsw_read_dcomp()
1262 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1268 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in hsw_disable_lcpll()
1272 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1306 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1329 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1339 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in hsw_restore_lcpll()
1812 u32 status = intel_de_read(display, DPIO_PHY_STATUS); in chv_phy_control_init()
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H A Dg4x_dp.c186 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
259 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
284 val = intel_de_read(display, dp_reg); in g4x_dp_port_enabled()
352 tmp = intel_de_read(display, intel_dp->output_reg); in intel_dp_get_config()
357 u32 trans_dp = intel_de_read(display, in intel_dp_get_config()
425 (intel_de_read(display, intel_dp->output_reg) & in intel_dp_link_down()
681 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); in intel_enable_dp()
1188 return intel_de_read(display, SDEISR) & bit; in ibx_digital_port_connected()
1211 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; in g4x_digital_port_connected()
1219 return intel_de_read(display, DEISR) & bit; in ilk_digital_port_connected()
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H A Dintel_tv.c919 u32 tmp = intel_de_read(display, TV_CTL); in intel_tv_get_hw_state()
1106 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_get_config()
1107 hctl1 = intel_de_read(display, TV_H_CTL_1); in intel_tv_get_config()
1108 hctl3 = intel_de_read(display, TV_H_CTL_3); in intel_tv_get_config()
1109 vctl1 = intel_de_read(display, TV_V_CTL_1); in intel_tv_get_config()
1110 vctl2 = intel_de_read(display, TV_V_CTL_2); in intel_tv_get_config()
1145 tmp = intel_de_read(display, TV_WIN_POS); in intel_tv_get_config()
1149 tmp = intel_de_read(display, TV_WIN_SIZE); in intel_tv_get_config()
1452 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_pre_enable()
1637 tv_dac = intel_de_read(display, TV_DAC); in intel_tv_detect_type()
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H A Dintel_ddi.c689 ctl = intel_de_read(dev_priv, in intel_ddi_disable_transcoder_func()
827 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
867 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
1571 return !(intel_de_read(i915, reg) & clk_off); in _icl_ddi_is_clock_enabled()
1818 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); in jsl_ddi_tc_is_clock_enabled()
1987 tmp = intel_de_read(display, DPLL_CTRL2); in skl_ddi_get_pll()
3436 val = intel_de_read(dev_priv, reg); in intel_ddi_enable_hdmi()
3913 u32 ctl2 = intel_de_read(dev_priv, in bdw_transcoder_master_readout()
3921 u32 ctl = intel_de_read(dev_priv, in bdw_transcoder_master_readout()
4046 intel_de_read(display, in intel_ddi_read_func_ctl_dp_sst()
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H A Dintel_hdmi.c286 u32 val = intel_de_read(display, reg); in ibx_write_infoframe()
339 u32 val = intel_de_read(display, reg); in ibx_infoframes_enabled()
361 u32 val = intel_de_read(display, reg); in cpt_write_infoframe()
435 u32 val = intel_de_read(display, reg); in vlv_write_infoframe()
480 *data++ = intel_de_read(display, in vlv_read_infoframe()
556 *data++ = intel_de_read(display, in hsw_read_infoframe()
564 u32 val = intel_de_read(display, in hsw_infoframes_enabled()
872 u32 val = intel_de_read(display, reg); in g4x_set_infoframes()
1059 u32 val = intel_de_read(display, reg); in ibx_set_infoframes()
1117 u32 val = intel_de_read(display, reg); in cpt_set_infoframes()
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H A Dintel_vga.c34 if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) in intel_vga_disable()
53 if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) { in intel_vga_redisable_power_on()
H A Dintel_overlay.c335 tmp = intel_de_read(display, DOVSTA); in intel_overlay_continue()
964 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); in update_pfit_vscale_ratio()
966 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
1309 attrs->gamma0 = intel_de_read(display, OGAMC0); in intel_overlay_attrs_ioctl()
1310 attrs->gamma1 = intel_de_read(display, OGAMC1); in intel_overlay_attrs_ioctl()
1311 attrs->gamma2 = intel_de_read(display, OGAMC2); in intel_overlay_attrs_ioctl()
1312 attrs->gamma3 = intel_de_read(display, OGAMC3); in intel_overlay_attrs_ioctl()
1313 attrs->gamma4 = intel_de_read(display, OGAMC4); in intel_overlay_attrs_ioctl()
1314 attrs->gamma5 = intel_de_read(display, OGAMC5); in intel_overlay_attrs_ioctl()
1495 error->dovsta = intel_de_read(display, DOVSTA); in intel_overlay_snapshot_capture()
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