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Searched refs:intel_de_posting_read (Results 1 – 25 of 32) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c496 intel_de_posting_read(display, reg); in intel_fdi_normal_train()
548 intel_de_posting_read(display, reg); in ilk_fdi_link_train()
630 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
659 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
710 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
767 intel_de_posting_read(display, reg); in ivb_manual_fdi_link_train()
809 intel_de_posting_read(display, reg); in ivb_manual_fdi_link_train()
1039 intel_de_posting_read(display, reg); in ilk_fdi_pll_enable()
1044 intel_de_posting_read(display, reg); in ilk_fdi_pll_enable()
1095 intel_de_posting_read(display, reg); in ilk_fdi_disable()
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H A Dg4x_hdmi.c63 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
234 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in g4x_hdmi_enable_port()
297 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
299 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
312 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
319 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
321 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
359 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
366 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
397 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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H A Dg4x_dp.c216 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
231 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
249 intel_de_posting_read(display, DP_A); in ilk_edp_pll_off()
440 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
444 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
464 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
468 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
621 intel_de_posting_read(display, intel_dp->output_reg); in cpt_set_link_train()
649 intel_de_posting_read(display, intel_dp->output_reg); in g4x_set_link_train()
671 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_enable_port()
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H A Dintel_fifo_underrun.c108 intel_de_posting_read(display, reg); in i9xx_check_fifo_underruns()
128 intel_de_posting_read(display, reg); in i9xx_set_fifo_underrun_reporting()
162 intel_de_posting_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
232 intel_de_posting_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
H A Dintel_pps.c152 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
155 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
776 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
847 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
989 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1005 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1017 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1064 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1110 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1131 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
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H A Dintel_pch_refclk.c618 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
637 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
648 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
662 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
H A Dintel_hdmi.c313 intel_de_posting_read(display, reg); in ibx_write_infoframe()
391 intel_de_posting_read(display, reg); in cpt_write_infoframe()
463 intel_de_posting_read(display, reg); in vlv_write_infoframe()
900 intel_de_posting_read(display, reg); in g4x_set_infoframes()
920 intel_de_posting_read(display, reg); in g4x_set_infoframes()
1074 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1095 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1144 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1202 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1232 intel_de_posting_read(display, reg); in intel_hdmi_fastset_infoframes()
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H A Dintel_pipe_crc.c619 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_set_crc_source()
654 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_enable_pipe_crc()
669 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_disable_pipe_crc()
H A Dintel_dkl_phy.c111 intel_de_posting_read(display, DKL_REG_MMIO(reg)); in intel_dkl_phy_posting_read()
H A Dintel_vga.c46 intel_de_posting_read(display, vga_reg); in intel_vga_disable()
H A Dintel_backlight.c509 intel_de_posting_read(display, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
548 intel_de_posting_read(display, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
562 intel_de_posting_read(display, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
593 intel_de_posting_read(display, BLC_PWM_CTL); in i9xx_enable_backlight()
638 intel_de_posting_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
672 intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
723 intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
754 intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
H A Dintel_dpll_mgr.c577 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_enable()
586 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_enable()
596 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_disable()
700 intel_de_posting_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
711 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_enable()
722 intel_de_posting_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
739 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_disable()
1377 intel_de_posting_read(display, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1392 intel_de_posting_read(display, regs[id].cfgcr1); in skl_ddi_pll_enable()
1419 intel_de_posting_read(display, regs[id].ctl); in skl_ddi_pll_disable()
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H A Dintel_dvo.c196 intel_de_posting_read(i915, DVO(port)); in intel_disable_dvo()
213 intel_de_posting_read(i915, DVO(port)); in intel_enable_dvo()
H A Dintel_dpll.c1865 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1883 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
2012 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in _vlv_enable_pll()
2042 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); in vlv_enable_pll()
2211 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); in chv_enable_pll()
2268 intel_de_posting_read(display, DPLL(display, pipe)); in vlv_disable_pll()
2287 intel_de_posting_read(display, DPLL(display, pipe)); in chv_disable_pll()
2313 intel_de_posting_read(display, DPLL(display, pipe)); in i9xx_disable_pll()
H A Dintel_de.h77 #define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__) macro
H A Dintel_crt.c515 intel_de_posting_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
741 intel_de_posting_read(display, in intel_crt_load_detect()
984 intel_de_posting_read(display, crt->adpa_reg); in intel_crt_reset()
H A Dhsw_ips.c87 intel_de_posting_read(display, IPS_CTL); in hsw_ips_disable()
H A Dintel_display_irq.c149 intel_de_posting_read(display, DEIMR); in ilk_update_display_irq()
191 intel_de_posting_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
223 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
263 intel_de_posting_read(display, SDEIMR); in ibx_display_interrupt_update()
342 intel_de_posting_read(display, reg); in i915_enable_pipestat()
366 intel_de_posting_read(display, reg); in i915_disable_pipestat()
H A Dintel_display_power.c1050 intel_de_posting_read(display, reg); in gen9_dbuf_slice_set()
1243 intel_de_posting_read(display, D_COMP_BDW); in hsw_write_dcomp()
1277 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1293 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1321 intel_de_posting_read(display, LCPLL_CTL); in hsw_restore_lcpll()
H A Dintel_lvds.c332 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
355 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
H A Dintel_gmbus.c292 intel_de_posting_read(display, bus->gpio_reg); in set_clock()
309 intel_de_posting_read(display, bus->gpio_reg); in set_data()
H A Dicl_dsi.c368 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
374 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
381 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
678 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
H A Dvlv_dsi_pll.c547 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
H A Dintel_display.c544 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in intel_enable_transcoder()
2954 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in i9xx_set_pipeconf()
3150 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in ilk_set_pipeconf()
3179 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); in hsw_set_transconf()
8189 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8202 intel_de_posting_read(display, DPLL(display, pipe)); in i830_enable_pipe()
8207 intel_de_posting_read(display, TRANSCONF(display, pipe)); in i830_enable_pipe()
8231 intel_de_posting_read(display, TRANSCONF(display, pipe)); in i830_disable_pipe()
8236 intel_de_posting_read(display, DPLL(display, pipe)); in i830_disable_pipe()
H A Dintel_tv.c1632 intel_de_posting_read(display, TV_DAC); in intel_tv_detect_type()
1664 intel_de_posting_read(display, TV_CTL); in intel_tv_detect_type()

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