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Searched refs:int_sel (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/mfd/
H A Dezx-pcap.c175 u32 msr, isr, int_sel, service; in pcap_isr_work() local
184 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel); in pcap_isr_work()
185 isr &= ~int_sel; in pcap_isr_work()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_vi.h475 enum RELEASE_MEM_int_sel_enum int_sel:3; member
H A Dkfd_packet_manager_vi.c290 packet->bitfields3.int_sel = in pm_release_mem_vi()
H A Dkfd_pm4_headers_ai.h540 enum mec_release_mem_int_sel_enum int_sel:3; member
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2122 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_gfx() local
2148 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2169 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v7_0_ring_emit_fence_compute() local
2177 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
H A Dgfx_v8_0.c6134 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_gfx() local
6163 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()
6231 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v8_0_ring_emit_fence_compute() local
6240 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
H A Dgfx_v6_0.c1822 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v6_0_ring_emit_fence() local
1841 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); in gfx_v6_0_ring_emit_fence()
H A Dgfx_v9_4_3.c2840 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_4_3_ring_emit_fence() local
2853 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_4_3_ring_emit_fence()
H A Dgfx_v12_0.c4362 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v12_0_ring_emit_fence() local
4372 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v12_0_ring_emit_fence()
H A Dgfx_v11_0.c5752 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v11_0_ring_emit_fence() local
5764 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
H A Dgfx_v9_0.c5541 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v9_0_ring_emit_fence() local
5561 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v9_0_ring_emit_fence()
H A Dgfx_v10_0.c8681 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; in gfx_v10_0_ring_emit_fence() local
8693 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v10_0_ring_emit_fence()