Searched refs:inst_header (Results 1 – 3 of 3) sorted by relevance
76 struct amdgpu_reg_inst_header inst_header; member89 struct amdgpu_reg_inst_header inst_header; member102 struct amdgpu_reg_inst_header inst_header; member121 struct amdgpu_reg_inst_header inst_header; member
909 pcie_regs->inst_header.instance = 0; in aqua_vanjaram_read_pcie_state()910 pcie_regs->inst_header.state = AMDGPU_INST_S_OK; in aqua_vanjaram_read_pcie_state()911 pcie_regs->inst_header.num_smn_regs = NUM_PCIE_SMN_REGS; in aqua_vanjaram_read_pcie_state()1003 xgmi_regs->inst_header.instance = inst++; in aqua_vanjaram_read_xgmi_state()1005 xgmi_regs->inst_header.state = AMDGPU_INST_S_OK; in aqua_vanjaram_read_xgmi_state()1006 xgmi_regs->inst_header.num_smn_regs = NUM_XGMI_SMN_REGS; in aqua_vanjaram_read_xgmi_state()1077 wafl_regs->inst_header.instance = inst++; in aqua_vanjaram_read_wafl_state()1079 wafl_regs->inst_header.state = AMDGPU_INST_S_OK; in aqua_vanjaram_read_wafl_state()1202 usr_regs->inst_header.instance = inst++; in aqua_vanjaram_read_usr_state()1203 usr_regs->inst_header.state = AMDGPU_INST_S_OK; in aqua_vanjaram_read_usr_state()[all …]
1382 u32 inst_header = *dw; in dump_mi_command() local1383 u32 numdw = instr_dw(inst_header); in dump_mi_command()1384 u32 opcode = REG_FIELD_GET(MI_OPCODE, inst_header); in dump_mi_command()1388 switch (inst_header & MI_OPCODE) { in dump_mi_command()1398 drm_printf(p, "[%#010x] MI_TOPOLOGY_FILTER\n", inst_header); in dump_mi_command()1402 drm_printf(p, "[%#010x] MI_BATCH_BUFFER_END\n", inst_header); in dump_mi_command()1414 switch (inst_header & MI_OPCODE) { in dump_mi_command()1417 inst_header, (numdw - 1) / 2); in dump_mi_command()1424 inst_header, in dump_mi_command()1437 drm_printf(p, "[%#010x] MI_FORCE_WAKEUP\n", inst_header); in dump_mi_command()[all …]