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Searched refs:idxmsk64 (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/arch/x86/events/intel/
H A Dcore.c3745 c2->idxmsk64 &= x86_pmu.lbr_counters; in intel_get_event_constraints()
3746 c2->weight = hweight64(c2->idxmsk64); in intel_get_event_constraints()
4536 if (c->idxmsk64 & (1U << 2)) in hsw_get_event_constraints()
4575 if (c->idxmsk64 & BIT_ULL(0)) in glc_get_event_constraints()
4635 c->idxmsk64 &= ~(1ULL << 3); in tfa_get_event_constraints()
4681 switch (c->idxmsk64 & 0x3ull) { in cmt_get_event_constraints()
6418 c->idxmsk64 = 0; in intel_pmu_check_event_constraints()
6419 c->weight = hweight64(c->idxmsk64); in intel_pmu_check_event_constraints()
6425 c->idxmsk64 &= intel_ctrl; in intel_pmu_check_event_constraints()
6432 c->idxmsk64 |= cntr_mask; in intel_pmu_check_event_constraints()
[all …]
/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c612 c->idxmsk64 |= x86_pmu.cntr_mask64; in zhaoxin_pmu_init()
/linux-6.15/arch/x86/events/
H A Dperf_event.h54 u64 idxmsk64; member
365 { .idxmsk64 = (n) }, \
H A Dcore.c882 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { in __perf_sched_find_counter()