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Searched refs:i915_reg_t (Results 1 – 25 of 98) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_de.h22 __intel_de_read(struct intel_display *display, i915_reg_t reg) in __intel_de_read()
37 intel_de_read8(struct intel_display *display, i915_reg_t reg) in intel_de_read8()
52 i915_reg_t lower_reg, i915_reg_t upper_reg) in intel_de_read64_2x32()
91 __intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg, in __intel_de_rmw_nowl()
115 i915_reg_t reg, in __intel_de_wait_for_register_nowl()
124 i915_reg_t reg, in __intel_de_wait_for_register_atomic_nowl()
133 intel_de_wait(struct intel_display *display, i915_reg_t reg, in intel_de_wait()
149 intel_de_wait_fw(struct intel_display *display, i915_reg_t reg, in intel_de_wait_fw()
165 intel_de_wait_custom(struct intel_display *display, i915_reg_t reg, in intel_de_wait_custom()
208 __intel_de_read_fw(struct intel_display *display, i915_reg_t reg) in __intel_de_read_fw()
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H A Dintel_sdvo.h19 i915_reg_t sdvo_reg, enum pipe *pipe);
21 i915_reg_t reg, enum port port);
24 i915_reg_t sdvo_reg, enum pipe *pipe) in intel_sdvo_port_enabled()
29 i915_reg_t reg, enum port port) in intel_sdvo_init()
H A Dg4x_dp.h23 i915_reg_t dp_reg, enum port port,
26 i915_reg_t output_reg, enum port port);
33 i915_reg_t dp_reg, int port, in g4x_dp_port_enabled()
39 i915_reg_t output_reg, int port) in g4x_dp_init()
H A Dintel_dsb.h36 i915_reg_t reg, u32 val);
38 i915_reg_t reg, u32 val);
40 i915_reg_t reg, u32 mask, u32 val);
58 i915_reg_t reg, u32 mask, u32 val,
H A Dintel_dp_aux.c59 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); in intel_dp_aux_wait_done()
246 i915_reg_t ch_ctl, ch_data[5]; in intel_dp_aux_xfer()
541 static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) in vlv_aux_ctl_reg()
557 static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) in vlv_aux_data_reg()
573 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) in g4x_aux_ctl_reg()
589 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) in g4x_aux_data_reg()
605 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) in ilk_aux_ctl_reg()
623 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) in ilk_aux_data_reg()
641 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) in skl_aux_ctl_reg()
679 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) in tgl_aux_ctl_reg()
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H A Dintel_vga.c17 static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) in intel_vga_cntrl_reg()
31 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); in intel_vga_disable()
51 i915_reg_t vga_reg = intel_vga_cntrl_reg(display); in intel_vga_redisable_power_on()
H A Dg4x_hdmi.h20 i915_reg_t hdmi_reg, enum port port);
25 i915_reg_t hdmi_reg, int port) in g4x_hdmi_init()
H A Dintel_crt.h17 i915_reg_t adpa_reg, enum pipe *pipe);
22 i915_reg_t adpa_reg, enum pipe *pipe) in intel_crt_port_enabled()
H A Dintel_lvds.h18 i915_reg_t lvds_reg, enum pipe *pipe);
24 i915_reg_t lvds_reg, enum pipe *pipe) in intel_lvds_port_enabled()
H A Dintel_dmc_wl.h36 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg);
37 void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg);
H A Dintel_display.h484 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
485 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
488 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
489 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
H A Dintel_pch_display.c42 i915_reg_t dp_reg) in assert_pch_dp_disabled()
62 i915_reg_t hdmi_reg) in assert_pch_hdmi_disabled()
121 enum port port, i915_reg_t hdmi_reg) in ibx_sanitize_pch_hdmi_port()
140 enum port port, i915_reg_t dp_reg) in ibx_sanitize_pch_dp_port()
255 i915_reg_t reg; in ilk_enable_pch_transcoder()
322 i915_reg_t reg; in ilk_disable_pch_transcoder()
427 i915_reg_t reg = TRANS_DP_CTL(pipe); in ilk_pch_enable()
H A Dintel_dmc_wl.c230 static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, in intel_dmc_wl_reg_in_range()
246 i915_reg_t reg, in intel_dmc_wl_check_range()
437 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) in intel_dmc_wl_get()
470 void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg) in intel_dmc_wl_put()
H A Dintel_pps.c492 i915_reg_t pp_ctrl;
493 i915_reg_t pp_stat;
494 i915_reg_t pp_on;
495 i915_reg_t pp_off;
496 i915_reg_t pp_div;
528 static i915_reg_t
538 static i915_reg_t
612 i915_reg_t pp_stat_reg, pp_ctrl_reg; in wait_panel_status()
962 i915_reg_t pp_ctrl_reg; in intel_pps_on_unlocked()
1037 i915_reg_t pp_ctrl_reg; in intel_pps_off_unlocked()
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/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h35 i915_reg_t i915_reg) in intel_uncore_read()
43 i915_reg_t i915_reg) in intel_uncore_read8()
51 i915_reg_t i915_reg) in intel_uncore_read16()
60 i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg) in intel_uncore_read64_2x32()
78 i915_reg_t i915_reg) in intel_uncore_posting_read()
86 i915_reg_t i915_reg, u32 val) in intel_uncore_write()
102 i915_reg_t i915_reg, u32 mask, in intel_wait_for_register()
112 i915_reg_t i915_reg, u32 mask, in intel_wait_for_register_fw()
143 i915_reg_t i915_reg) in intel_uncore_read_fw()
151 i915_reg_t i915_reg, u32 val) in intel_uncore_write_fw()
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/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_uncore.h98 i915_reg_t r);
100 i915_reg_t r);
103 i915_reg_t r, bool trace);
105 i915_reg_t r, bool trace);
287 i915_reg_t reg,
295 i915_reg_t reg, in intel_wait_for_register()
305 i915_reg_t reg,
313 i915_reg_t reg, in intel_wait_for_register_fw()
327 i915_reg_t reg) \
359 i915_reg_t reg) \
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H A Di915_perf_types.h50 i915_reg_t oa_head_ptr;
51 i915_reg_t oa_tail_ptr;
52 i915_reg_t oa_buffer;
53 i915_reg_t oa_ctx_ctrl;
54 i915_reg_t oa_ctrl;
55 i915_reg_t oa_debug;
56 i915_reg_t oa_status;
73 i915_reg_t addr;
H A Di915_reg_defs.h265 } i915_reg_t; typedef
267 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
283 _Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
289 i915_reg_t imr;
290 i915_reg_t ier;
291 i915_reg_t iir;
298 i915_reg_t emr;
299 i915_reg_t eir;
H A Di915_hwmon.c35 i915_reg_t gt_perf_status;
36 i915_reg_t pkg_temp;
37 i915_reg_t pkg_power_sku_unit;
38 i915_reg_t pkg_power_sku;
39 i915_reg_t pkg_rapl_limit;
40 i915_reg_t energy_status_all;
41 i915_reg_t energy_status_tile;
42 i915_reg_t fan_speed;
79 i915_reg_t reg, u32 clear, u32 set) in hwm_locked_with_pm_intel_uncore_rmw()
142 i915_reg_t rgaddr; in hwm_energy()
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H A Di915_ioctl.c23 i915_reg_t offset_ldw;
24 i915_reg_t offset_udw;
H A Dintel_uncore.c1181 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) in gen6_reg_write_fw_domains()
1761 const i915_reg_t reg, in __unclaimed_reg_debug()
1775 const i915_reg_t reg, in __unclaimed_previous_reg_debug()
1787 const i915_reg_t reg, const bool read) in unclaimed_reg_debug_header()
1803 const i915_reg_t reg, const bool read) in unclaimed_reg_debug_footer()
1814 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
2062 i915_reg_t reg_set, in __fw_domain_init()
2063 i915_reg_t reg_ack) in __fw_domain_init()
2724 i915_reg_t reg, in __intel_wait_for_register_fw()
2773 i915_reg_t reg, in __intel_wait_for_register()
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/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm_irq.c18 i915_reg_t reg; in write_pm_imr()
65 i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_gt_pm_reset_iir()
79 i915_reg_t reg; in write_pm_ier()
H A Dintel_workarounds_types.h17 i915_reg_t reg;
/linux-6.15/drivers/gpu/drm/i915/selftests/
H A Dmock_uncore.c29 nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
H A Dintel_uncore.c211 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset); in live_forcewake_ops()
303 i915_reg_t reg = { offset }; in live_forcewake_domains()
314 i915_reg_t reg = { offset }; in live_forcewake_domains()

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