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Searched refs:i915_mmio_reg_offset (Results 1 – 25 of 52) sorted by relevance

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/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h37 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read()
45 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read8()
53 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read16()
80 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_posting_read()
88 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_write()
96 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_rmw()
105 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register()
115 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_wait_for_register_fw()
126 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in __intel_wait_for_register()
145 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); in intel_uncore_read_fw()
[all …]
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c173 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
351 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
353 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
380 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
386 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
388 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
469 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
527 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
538 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
544 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
H A Dedid.c386 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
388 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
416 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
418 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
420 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
422 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
H A Dhandlers.c179 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
812 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
891 u32 start = i915_mmio_reg_offset(_start); in calc_index()
892 u32 next = i915_mmio_reg_offset(_next); in calc_index()
893 u32 end = i915_mmio_reg_offset(_end); in calc_index()
1095 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
1098 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
1101 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
1199 offset != i915_mmio_reg_offset(port_index ? in dp_aux_ch_ctl_mmio_write()
2154 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
[all …]
H A Dscheduler.c92 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
97 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
98 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
114 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
274 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
278 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
[all …]
H A Dmmio_context.c236 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
266 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
293 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
549 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c1266 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1274 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1275 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1281 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1319 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1335 *cs++ = i915_mmio_reg_offset(DRAW_WATERMARK); in dg2_emit_draw_watermark_setting()
1345 *cs++ = i915_mmio_reg_offset(GEN12_CS_DEBUG_MODE2); in gen12_invalidate_state_cache()
1642 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1648 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
1657 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); in gen8_emit_flush_coherentl3_wa()
[all …]
H A Dselftest_lrc.c304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
314 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
319 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
329 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
339 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
364 i915_mmio_reg_offset(RING_BB_OFFSET(engine->mmio_base)), in live_lrc_fixed()
444 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base)); in __live_lrc_state()
451 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)); in __live_lrc_state()
[all …]
H A Dselftest_workarounds.c157 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
184 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
465 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
520 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
870 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
906 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
961 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
965 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
989 i915_mmio_reg_offset(reg), a, b); in result_eq()
1011 i915_mmio_reg_offset(reg), a); in result_neq()
[all …]
H A Dintel_workarounds.c148 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
187 i915_mmio_reg_offset(wa_->reg), in _wa_add()
206 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
207 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
208 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
209 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
1013 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1723 name, from, i915_mmio_reg_offset(wa->reg), in wa_verify()
2154 i915_mmio_reg_offset(wa->reg)); in intel_engine_apply_whitelist()
2160 i915_mmio_reg_offset(RING_NOPID(base))); in intel_engine_apply_whitelist()
[all …]
H A Dintel_ring_submission.c697 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
701 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
706 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
711 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
759 *cs++ = i915_mmio_reg_offset( in mi_set_context()
814 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
821 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
856 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
H A Dselftest_rps.c103 *cs++ = i915_mmio_reg_offset(CS_GPR(i)); in create_spin_counter()
105 *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4; in create_spin_counter()
110 *cs++ = i915_mmio_reg_offset(CS_GPR(INC)); in create_spin_counter()
125 *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT)); in create_spin_counter()
208 i915_mmio_reg_offset(BXT_RP_STATE_CAP), in show_pstate_limits()
213 i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS), in show_pstate_limits()
H A Dselftest_mocs.c152 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in read_l3cc_table()
197 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); in check_l3cc_table()
H A Dgen8_engine_cs.c208 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
216 *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; in gen12_emit_aux_table_inv()
501 *cs++ = i915_mmio_reg_offset(RING_PREDICATE_RESULT(0)); in __xehp_emit_bb_start()
H A Dgen7_renderclear.c400 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); in emit_batch()
406 batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1)); in emit_batch()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg_defs.h282 #define i915_mmio_reg_offset(r) \ macro
284 #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
H A Dintel_uncore.h329 u32 offset = i915_mmio_reg_offset(reg); \
339 u32 offset = i915_mmio_reg_offset(reg); \
519 readl(base + i915_mmio_reg_offset(reg))
521 writel(value, base + i915_mmio_reg_offset(reg))
H A Dintel_uncore_trace.h31 __entry->reg = i915_mmio_reg_offset(reg);
H A Di915_perf.c1336 *cs++ = i915_mmio_reg_offset(reg); in __store_reg_to_mem()
1927 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
2028 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
2042 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
2046 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
2066 *cs++ = i915_mmio_reg_offset(mi_predicate_result); in alloc_noa_wait()
2109 *cs++ = i915_mmio_reg_offset(mi_predicate_result); in alloc_noa_wait()
2172 *cs++ = i915_mmio_reg_offset(reg_data[i].addr); in write_cs_mi_lri()
2421 u32 mmio = i915_mmio_reg_offset(reg); in oa_config_flex_reg()
2521 *cs++ = i915_mmio_reg_offset(flex->reg); in gen8_load_flex()
[all …]
H A Di915_ioctl.c55 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
H A Dintel_device_info.c348 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), in intel_ipver_early_init()
356 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), in intel_ipver_early_init()
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c340 i915_mmio_reg_offset(reg), \
366 return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags); in guc_mcr_reg_add()
421 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false); in guc_mmio_regset_init()
422 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false); in guc_mmio_regset_init()
423 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false); in guc_mmio_regset_init()
424 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false); in guc_mmio_regset_init()
425 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false); in guc_mmio_regset_init()
426 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false); in guc_mmio_regset_init()
427 ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false); in guc_mmio_regset_init()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dsb.c262 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); in intel_dsb_prev_ins_is_write()
307 i915_mmio_reg_offset(reg)); in intel_dsb_reg_write_indexed()
329 i915_mmio_reg_offset(reg)); in intel_dsb_reg_write()
347 i915_mmio_reg_offset(reg)); in intel_dsb_reg_write_masked()
487 i915_mmio_reg_offset(reg)); in intel_dsb_poll()
H A Dintel_dmc.c517 u32 offset = i915_mmio_reg_offset(reg); in is_dmc_evt_ctl_reg()
518 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); in is_dmc_evt_ctl_reg()
519 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_ctl_reg()
527 u32 offset = i915_mmio_reg_offset(reg); in is_dmc_evt_htp_reg()
528 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); in is_dmc_evt_htp_reg()
529 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); in is_dmc_evt_htp_reg()
/linux-6.15/drivers/gpu/drm/xe/display/ext/
H A Di915_irq.c37 i915_mmio_reg_offset(reg), val); in gen2_assert_iir_is_zero()

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