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Searched refs:hw_ste_p (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_ste_v1.h142 bool dr_ste_v1_is_miss_addr_set(u8 *hw_ste_p);
143 void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr);
144 u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p);
145 void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask);
146 u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p);
147 void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type);
148 u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p);
151 void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size);
152 void dr_ste_v1_set_reparse(u8 *hw_ste_p);
158 void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action);
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H A Ddr_ste.h150 void (*ste_init)(u8 *hw_ste_p, u16 lu_type,
152 void (*set_next_lu_type)(u8 *hw_ste_p, u16 lu_type);
153 u16 (*get_next_lu_type)(u8 *hw_ste_p);
154 bool (*is_miss_addr_set)(u8 *hw_ste_p);
155 void (*set_miss_addr)(u8 *hw_ste_p, u64 miss_addr);
156 u64 (*get_miss_addr)(u8 *hw_ste_p);
158 void (*set_byte_mask)(u8 *hw_ste_p, u16 byte_mask);
159 u16 (*get_byte_mask)(u8 *hw_ste_p);
203 void (*set_encap)(u8 *hw_ste_p, u8 *d_action,
207 void (*set_pop_vlan)(u8 *hw_ste_p, u8 *s_action,
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H A Ddr_ste_v3.c7 static void dr_ste_v3_set_encap(u8 *hw_ste_p, u8 *d_action, in dr_ste_v3_set_encap() argument
17 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v3_set_encap()
32 static void dr_ste_v3_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, in dr_ste_v3_set_pop_vlan() argument
43 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v3_set_pop_vlan()
46 static void dr_ste_v3_set_encap_l3(u8 *hw_ste_p, in dr_ste_v3_set_encap_l3() argument
67 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v3_set_encap_l3()
70 static void dr_ste_v3_set_rx_decap(u8 *hw_ste_p, u8 *s_action) in dr_ste_v3_set_rx_decap() argument
79 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v3_set_rx_decap()
82 static void dr_ste_v3_set_insert_hdr(u8 *hw_ste_p, u8 *d_action, in dr_ste_v3_set_insert_hdr() argument
102 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v3_set_insert_hdr()
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H A Ddr_ste_v0.c241 static u8 dr_ste_v0_get_entry_type(u8 *hw_ste_p) in dr_ste_v0_get_entry_type() argument
255 static u64 dr_ste_v0_get_miss_addr(u8 *hw_ste_p) in dr_ste_v0_get_miss_addr() argument
269 static u16 dr_ste_v0_get_byte_mask(u8 *hw_ste_p) in dr_ste_v0_get_byte_mask() argument
271 return MLX5_GET(ste_general, hw_ste_p, byte_mask); in dr_ste_v0_get_byte_mask()
305 dr_ste_v0_set_entry_type(hw_ste_p, entry_type); in dr_ste_v0_init_full()
306 dr_ste_v0_set_lu_type(hw_ste_p, lu_type); in dr_ste_v0_init_full()
341 MLX5_SET(ste_sx_transmit, hw_ste_p, go_back, 1); in dr_ste_v0_set_go_back_bit()
347 MLX5_SET(ste_sx_transmit, hw_ste_p, action_type, in dr_ste_v0_set_tx_push_vlan()
354 dr_ste_v0_set_go_back_bit(hw_ste_p); in dr_ste_v0_set_tx_push_vlan()
360 MLX5_SET(ste_sx_transmit, hw_ste_p, action_type, in dr_ste_v0_set_tx_encap()
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H A Ddr_ste_v1.c223 u8 *tag = hw_ste_p + DR_STE_SIZE_CTRL; in dr_ste_v1_prepare_for_postsend()
252 void dr_ste_v1_set_reparse(u8 *hw_ste_p) in dr_ste_v1_set_reparse() argument
266 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_encap()
286 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_insert_hdr()
301 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_remove_hdr()
314 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_push_vlan()
327 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_pop_vlan()
348 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_encap_l3()
360 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_rx_decap()
383 dr_ste_v1_set_reparse(hw_ste_p); in dr_ste_v1_set_accelerated_rewrite_actions()
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H A Ddr_ste.c27 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl) in mlx5dr_ste_calc_hash_index() argument
30 struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p; in mlx5dr_ste_calc_hash_index()
68 static u8 *dr_ste_get_tag(u8 *hw_ste_p) in dr_ste_get_tag() argument
70 struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p; in dr_ste_get_tag()
75 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask) in mlx5dr_ste_set_bit_mask() argument
95 u8 *hw_ste_p) in mlx5dr_ste_is_miss_addr_set() argument
101 return ste_ctx->is_miss_addr_set(hw_ste_p); in mlx5dr_ste_is_miss_addr_set()
105 u8 *hw_ste_p, u64 miss_addr) in mlx5dr_ste_set_miss_addr() argument
107 ste_ctx->set_miss_addr(hw_ste_p, miss_addr); in mlx5dr_ste_set_miss_addr()
394 u8 *hw_ste_p, u32 ste_size) in mlx5dr_ste_prepare_for_postsend() argument
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H A Ddr_types.h248 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
249 bool mlx5dr_ste_is_miss_addr_set(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p);
257 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
1397 u8 *hw_ste_p, u32 ste_size);