Home
last modified time | relevance | path

Searched refs:hsp (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/drivers/mailbox/
H A Dtegra-hsp.c255 tegra_hsp_writel(hsp, hsp->mask, in tegra_hsp_shared_irq()
293 db->channel.hsp = hsp; in tegra_hsp_doorbell_create()
478 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); in tegra_hsp_mailbox_send_data()
539 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); in tegra_hsp_mailbox_startup()
578 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); in tegra_hsp_mailbox_shutdown()
692 mb->channel.hsp = hsp; in tegra_hsp_add_mailboxes()
758 hsp->num_sm = (value >> hsp->soc->sm_shift) & hsp->soc->sm_mask; in tegra_hsp_probe()
759 hsp->num_ss = (value >> hsp->soc->ss_shift) & hsp->soc->ss_mask; in tegra_hsp_probe()
760 hsp->num_as = (value >> hsp->soc->as_shift) & hsp->soc->as_mask; in tegra_hsp_probe()
761 hsp->num_db = (value >> hsp->soc->db_shift) & hsp->soc->db_mask; in tegra_hsp_probe()
[all …]
H A DMakefile54 obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
/linux-6.15/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
59 <dt-bindings/mailbox/tegra186-hsp.h>
63 pattern: "^hsp@[0-9a-f]+$"
67 - const: nvidia,tegra186-hsp
68 - const: nvidia,tegra194-hsp
69 - const: nvidia,tegra264-hsp
71 - const: nvidia,tegra234-hsp
72 - const: nvidia,tegra194-hsp
112 #include <dt-bindings/mailbox/tegra186-hsp.h>
114 hsp_top0: hsp@3c00000 {
[all …]
/linux-6.15/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml26 - .../mailbox/nvidia,tegra186-hsp.yaml
142 #include <dt-bindings/mailbox/tegra186-hsp.h>
145 hsp_top0: hsp@3c00000 {
146 compatible = "nvidia,tegra186-hsp";
201 #include <dt-bindings/mailbox/tegra186-hsp.h>
/linux-6.15/drivers/video/fbdev/
H A Dcarminefb.c63 u32 hsp; member
106 .hsp = 672,
118 .hsp = 864,
372 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
381 hsp = par->res->hsp - 1; in set_display_parameters()
394 (hsp)); in set_display_parameters()
/linux-6.15/drivers/scsi/lpfc/
H A Dlpfc_nportdisc.c98 hsp->cls1.rcvDataSizeLsb); in lpfc_check_sparm()
105 hsp->cls1.rcvDataSizeLsb; in lpfc_check_sparm()
107 hsp->cls1.rcvDataSizeMsb; in lpfc_check_sparm()
115 hsp->cls2.rcvDataSizeLsb); in lpfc_check_sparm()
122 hsp->cls2.rcvDataSizeLsb; in lpfc_check_sparm()
124 hsp->cls2.rcvDataSizeMsb; in lpfc_check_sparm()
132 hsp->cls3.rcvDataSizeLsb); in lpfc_check_sparm()
139 hsp->cls3.rcvDataSizeLsb; in lpfc_check_sparm()
141 hsp->cls3.rcvDataSizeMsb; in lpfc_check_sparm()
152 hsp_value = (hsp->cmn.bbRcvSizeMsb << 8) | hsp->cmn.bbRcvSizeLsb; in lpfc_check_sparm()
[all …]
H A Dlpfc_ct.c2929 struct serv_parm *hsp = (struct serv_parm *)&vport->fc_sparam; in lpfc_fdmi_port_attr_max_frame() local
2932 (((uint32_t)hsp->cmn.bbRcvSizeMsb & 0x0F) << 8) | in lpfc_fdmi_port_attr_max_frame()
2933 (uint32_t)hsp->cmn.bbRcvSizeLsb); in lpfc_fdmi_port_attr_max_frame()
/linux-6.15/drivers/clk/imx/
H A Dclk-imx31.c39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
62 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in _mx31_clocks_init()
H A Dclk-imx35.c64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
/linux-6.15/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c48 static inline int hsp(struct fb_var_screeninfo *var) in hsp() function
251 pack((fbi->var.hsync_len - 1), hsp(&fbi->var)); in mb862xxfb_set_par()
438 unsigned long hsp, vsp, ht, vt; in mb862xxfb_init_fbinfo() local
461 hsp = (reg & 0xffff) + 1; in mb862xxfb_init_fbinfo()
463 fbi->var.right_margin = hsp - fbi->var.xres; in mb862xxfb_init_fbinfo()
464 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len; in mb862xxfb_init_fbinfo()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c203 uint8_t hsp; in dcn31_hpo_dp_stream_enc_set_stream_attribute() local
362 hsp = hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 0 : 0x80; in dcn31_hpo_dp_stream_enc_set_stream_attribute()
422 MSA_DATA_LANE_0, hsp | (hw_crtc_timing.h_sync_width >> 8), in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dimx35-clock.yaml24 hsp 5
H A Dimx31-clock.yaml26 hsp 7
/linux-6.15/Documentation/devicetree/bindings/serial/
H A Dnvidia,tegra194-tcu.yaml54 #include <dt-bindings/mailbox/tegra186-hsp.h>
/linux-6.15/drivers/atm/
H A Dhe.c1463 he_dev->hsp = dma_alloc_coherent(&he_dev->pci_dev->dev, in he_start()
1466 if (he_dev->hsp == NULL) { in he_start()
1565 if (he_dev->hsp) in he_stop()
1567 he_dev->hsp, he_dev->hsp_phys); in he_stop()
1643 he_dev->hsp->group[group].rbrq_tail); in he_service_rbrq()
1803 he_dev->hsp->group[group].tbrq_tail); in he_service_tbrq()
H A Dhe.h310 struct he_hsp *hsp; member
/linux-6.15/arch/arm64/boot/dts/nvidia/
H A Dtegra186-p3310.dtsi161 hsp@3c00000 {
H A Dtegra194.dtsi5 #include <dt-bindings/mailbox/tegra186-hsp.h>
1360 hsp_top0: hsp@3c00000 {
1361 compatible = "nvidia,tegra194-hsp";
1558 hsp_aon: hsp@c150000 {
1559 compatible = "nvidia,tegra194-hsp";
H A Dtegra186.dtsi5 #include <dt-bindings/mailbox/tegra186-hsp.h>
1194 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186-hsp";
H A Dtegra234.dtsi6 #include <dt-bindings/mailbox/tegra186-hsp.h>
3302 hsp_top0: hsp@3c00000 {
3303 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
3828 hsp_aon: hsp@c150000 {
3829 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
H A Dtegra186-p3509-0000+p3636-0001.dts715 hsp@3c00000 {