Home
last modified time | relevance | path

Searched refs:gpu_addr (Results 1 – 25 of 175) sorted by relevance

1234567

/linux-6.15/drivers/gpu/drm/radeon/
H A Dr600_dma.c150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
236 u64 gpu_addr; in r600_dma_ring_test() local
243 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
317 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
343 u64 gpu_addr; in r600_dma_ib_test() local
350 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ib_test()
359 ib.ptr[1] = lower_32_bits(gpu_addr); in r600_dma_ib_test()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
[all …]
H A Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
H A Dcik_sdma.c155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
232 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
651 u64 gpu_addr; in cik_sdma_ring_test() local
658 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
669 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
708 u64 gpu_addr; in cik_sdma_ib_test() local
715 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ib_test()
727 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ib_test()
[all …]
H A Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
H A Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
487 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
H A Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c157 uint64_t addr = table->gpu_addr; in vce_v4_0_mmsch_start()
235 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
237 upper_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
282 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
658 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
[all …]
H A Damdgpu_ih.c69 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init()
89 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init()
128 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
H A Dvcn_v2_0.c395 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
960 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
964 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
966 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1125 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1127 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1852 uint64_t addr = table->gpu_addr; in vcn_v2_0_start_mmsch()
2014 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2017 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2028 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
[all …]
H A Dvcn_v5_0_1.c334 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
336 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_1_mc_resume()
345 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
347 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_1_mc_resume()
361 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
363 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_1_mc_resume()
413 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
416 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
454 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + in vcn_v5_0_1_mc_resume_dpg_mode()
458 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + in vcn_v5_0_1_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_5.c1139 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode()
1143 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1145 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1316 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1318 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1353 uint64_t addr = table->gpu_addr; in vcn_v2_5_mmsch_start()
1453 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_sriov_start()
1503 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1506 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1516 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
[all …]
H A Dsi_dma.c74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
158 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
199 u64 gpu_addr; in si_dma_ring_test_ring() local
205 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring()
214 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
215 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
250 u64 gpu_addr; in si_dma_ring_test_ib() local
257 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib()
267 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
268 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
[all …]
H A Damdgpu_sa.c54 &sa_manager->bo, &sa_manager->gpu_addr, in amdgpu_sa_bo_manager_init()
76 amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr); in amdgpu_sa_bo_manager_fini()
113 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr); in amdgpu_sa_bo_dump_debug_info()
H A Duvd_v7_0.c694 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
696 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
734 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start()
836 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
838 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
1097 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start()
1101 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1103 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1333 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1336 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
[all …]
H A Dvcn_v1_0.c364 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
366 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
976 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
980 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
982 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1135 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode()
1139 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1141 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1373 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1375 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
[all …]
H A Dvcn_v3_0.c534 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
1148 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v3_0_start_dpg_mode()
1152 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1154 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1328 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1330 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1432 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1435 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1478 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
1492 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
[all …]
H A Dvce_v3_0.c283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start()
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
566 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
570 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
868 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
869 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
H A Dvcn_v5_0_0.c395 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
397 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
405 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
407 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
421 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
423 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
471 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
474 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
773 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start_dpg_mode()
929 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start()
[all …]
H A Dvcn_v4_0_3.c466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
940 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
942 upper_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
1037 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
1040 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
1051 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; in vcn_v4_0_3_start_sriov()
1081 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_3_start_sriov()
1110 ctx_addr = table->gpu_addr; in vcn_v4_0_3_start_sriov()
1302 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start()
[all …]
H A Dvcn_v4_0.c478 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
480 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
488 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
490 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
1401 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1404 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1415 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v4_0_start_sriov()
1429 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v4_0_start_sriov()
1449 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_start_sriov()
1478 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); in vcn_v4_0_start_sriov()
[all …]
H A Damdgpu_seq64.h41 int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr);
42 void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);
H A Dsdma_v2_4.c260 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
261 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
538 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local
544 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring()
554 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
555 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
591 u64 gpu_addr; in sdma_v2_4_ring_test_ib() local
598 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ib()
609 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
610 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
H A Damdgpu_object.h258 u64 *gpu_addr, void **cpu_addr);
262 u64 *gpu_addr, void **cpu_addr);
266 u64 *gpu_addr);
276 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
323 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr + in amdgpu_sa_bo_gpu_addr()
H A Dcik_sdma.c236 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
477 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
608 u64 gpu_addr; in cik_sdma_ring_test_ring() local
614 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
623 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
624 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
660 u64 gpu_addr; in cik_sdma_ring_test_ib() local
667 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ib()
678 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
679 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
[all …]
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; in allocate_hiq_mqd()
84 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in allocate_sdma_mqd()
285 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in kfd_get_hiq_xcc_mqd()

1234567