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/linux-6.15/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
143 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
140 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
190 gic: interrupt-controller@2f000000 { label
191 compatible = "arm,gic-v3";
206 compatible = "arm,gic-v3-its";
277 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
280 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
281 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dmorello-sdp.dts125 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
126 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
127 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
128 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.15/drivers/irqchip/
H A Dirq-gic.c522 gic_cpu_if_up(gic); in gic_cpu_init()
556 if (WARN_ON(!gic)) in gic_dist_save()
595 if (WARN_ON(!gic)) in gic_dist_restore()
642 if (WARN_ON(!gic)) in gic_cpu_save()
672 if (WARN_ON(!gic)) in gic_cpu_restore()
1196 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1197 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1212 gic); in gic_init_bases()
1243 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1422 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
[all …]
H A Dirq-gic-pm.c28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
/linux-6.15/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
212 interrupt-parent = <&gic>;
[all …]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
121 interrupt-parent = <&gic>;
144 interrupt-parent = <&gic>;
[all …]
/linux-6.15/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
120 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
121 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2m.dtsi33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
41 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
42 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
37 - arm,tc11mp-gic
42 - const: arm,gic-400
44 - arm,cortex-a15-gic
[all …]
H A Drenesas,rza1-irqc.yaml63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
77 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
73 const: mti,gic-timer
107 #include <dt-bindings/interrupt-controller/mips-gic.h>
111 compatible = "mti,gic";
119 compatible = "mti,gic-timer";
125 #include <dt-bindings/interrupt-controller/mips-gic.h>
129 compatible = "mti,gic";
135 compatible = "mti,gic-timer";
[all …]
H A Dfsl,ls-extirq.yaml122 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
131 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
132 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
133 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
134 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
135 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.15/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 { label
59 compatible = "arm,gic-v3";
71 compatible = "arm,gic-v3-its";
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
137 interrupt-parent = <&gic>;
/linux-6.15/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.15/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi147 interrupt-parent = <&gic>;
178 interrupt-parent = <&gic>;
209 interrupt-parent = <&gic>;
311 interrupt-parent = <&gic>;
508 interrupt-parent = <&gic>;
521 interrupt-parent = <&gic>;
581 interrupt-parent = <&gic>;
594 interrupt-parent = <&gic>;
607 interrupt-parent = <&gic>;
620 interrupt-parent = <&gic>;
[all …]
/linux-6.15/arch/mips/boot/dts/ralink/
H A Dmt7621.dtsi2 #include <dt-bindings/interrupt-controller/mips-gic.h>
186 interrupt-parent = <&gic>;
223 interrupt-parent = <&gic>;
241 interrupt-parent = <&gic>;
261 interrupt-parent = <&gic>;
307 interrupt-parent = <&gic>;
334 interrupt-parent = <&gic>;
338 gic: interrupt-controller@1fbc0000 { label
339 compatible = "mti,gic";
348 compatible = "mti,gic-timer";
[all …]
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
91 gic: interrupt-controller@7d001000 { label
92 compatible = "arm,cortex-a15-gic";
108 interrupt-parent = <&gic>;
115 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dhisilicon,kirin-pcie.yaml68 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
98 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
130 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.15/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi30 interrupt-parent = <&gic>;
84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux-6.15/arch/mips/boot/dts/img/
H A Dboston.dts7 #include <dt-bindings/interrupt-controller/mips-gic.h>
48 interrupt-parent = <&gic>;
78 interrupt-parent = <&gic>;
108 interrupt-parent = <&gic>;
181 gic: interrupt-controller@16120000 { label
182 compatible = "mti,gic";
189 compatible = "mti,gic-timer";
227 interrupt-parent = <&gic>;
/linux-6.15/include/linux/irqchip/
H A Darm-gic.h137 void gic_cpu_save(struct gic_chip_data *gic);
138 void gic_cpu_restore(struct gic_chip_data *gic);
139 void gic_dist_save(struct gic_chip_data *gic);
140 void gic_dist_restore(struct gic_chip_data *gic);
152 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
/linux-6.15/arch/mips/boot/dts/mti/
H A Dmalta.dts5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
/linux-6.15/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
47 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)

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