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Searched refs:gfx8 (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c110 update->plane_info->tiling_info.gfx8.num_banks, in update_surface_trace()
111 update->plane_info->tiling_info.gfx8.bank_width, in update_surface_trace()
112 update->plane_info->tiling_info.gfx8.bank_width_c, in update_surface_trace()
113 update->plane_info->tiling_info.gfx8.bank_height, in update_surface_trace()
115 update->plane_info->tiling_info.gfx8.tile_aspect, in update_surface_trace()
117 update->plane_info->tiling_info.gfx8.tile_split, in update_surface_trace()
118 update->plane_info->tiling_info.gfx8.tile_split_c, in update_surface_trace()
119 update->plane_info->tiling_info.gfx8.tile_mode, in update_surface_trace()
120 update->plane_info->tiling_info.gfx8.tile_mode_c); in update_surface_trace()
127 update->plane_info->tiling_info.gfx8.pipe_config, in update_surface_trace()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c103 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
451 GRPH_NUM_BANKS, info->gfx8.num_banks, in program_tiling()
452 GRPH_BANK_WIDTH, info->gfx8.bank_width, in program_tiling()
453 GRPH_BANK_HEIGHT, info->gfx8.bank_height, in program_tiling()
455 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
457 GRPH_PIPE_CONFIG, info->gfx8.pipe_config, in program_tiling()
458 GRPH_ARRAY_MODE, info->gfx8.array_mode, in program_tiling()
468 GRPH_NUM_BANKS, info->gfx8.num_banks, in program_tiling()
469 GRPH_BANK_WIDTH, info->gfx8.bank_width, in program_tiling()
472 GRPH_TILE_SPLIT, info->gfx8.tile_split, in program_tiling()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c170 set_reg_field_value(value, info->gfx8.num_banks, in program_tiling()
173 set_reg_field_value(value, info->gfx8.bank_width, in program_tiling()
176 set_reg_field_value(value, info->gfx8.bank_height, in program_tiling()
179 set_reg_field_value(value, info->gfx8.tile_aspect, in program_tiling()
182 set_reg_field_value(value, info->gfx8.tile_split, in program_tiling()
185 set_reg_field_value(value, info->gfx8.tile_mode, in program_tiling()
188 set_reg_field_value(value, info->gfx8.pipe_config, in program_tiling()
191 set_reg_field_value(value, info->gfx8.array_mode, in program_tiling()
207 set_reg_field_value(value, info->gfx8.bank_width_c, in program_tiling()
219 set_reg_field_value(value, info->gfx8.tile_mode_c, in program_tiling()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c195 tiling_info->gfx8.num_banks = num_banks; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
196 tiling_info->gfx8.array_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
198 tiling_info->gfx8.tile_split = tile_split; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
199 tiling_info->gfx8.bank_width = bankw; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
200 tiling_info->gfx8.bank_height = bankh; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
201 tiling_info->gfx8.tile_aspect = mtaspect; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
202 tiling_info->gfx8.tile_mode = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
206 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
209 tiling_info->gfx8.pipe_config = in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
H A Damdgpu_dm.c7563 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; in dm_validate_stream_and_context()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c105 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in dce60_should_enable_fbc()
/linux-6.15/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h417 } gfx8; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c2218 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()